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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [doc/] [mem_map.txt] - Blame information for rev 133

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Line No. Rev Author Line
1 131 jt_eaton
 
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io_module
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                 GPIO_0_IN      = 8000;
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                 GPIO_0_OE      = 8001;
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                 GPIO_0_OUT     = 8002;
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                 GPIO_1_IN      = 8004;
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                 GPIO_1_OE      = 8005;
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                 GPIO_1_OUT     = 8006;
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                 TIMER_0_START  = 8010;    TIMER_START:     rdata  = {4'h0,irq,trig,run,idle};
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                 TIMER_0_COUNT  = 8011;
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                 TIMER_0_END    = 8012;
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                 TIMER_1_START  = 8020;    TIMER_START:     rdata  = {4'h0,irq,trig,run,idle};
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                 TIMER_1_COUNT  = 8021;
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                 TIMER_1_END    = 8022;
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                 XMIT_DATA     =  8030;
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                 RCV_DATA      =  8031;
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                 CNTRL         =  8032;   // TX_IRQ_EN,RX_IRQ_EN,0,0,RTS,TX_BREAK,FORCE_PARITY,PARITY
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                 STATUS        =  8033;    {status[7:1],rx_data_avail};
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                 INT_IN         = 8040;  {ext_in[3:0],tx_irq,rx_irq,tim_1_irq,tim_0_irq}),
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                 IRQ_ENABLE     = 8041;
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                 NMI_ENABLE     = 8042;
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                 IRQ_ACT        = 8043;
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                 NMI_ACT        = 8044;
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