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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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wire [7:0]    irq_enable;
reg [7:0]    irq_act;
 
 
 
 
 
`VARIANT`MB
#(.IRQ_ENABLE_RST(IRQ_MODE))
vic_micro_reg
(
        .clk               ( clk          ),
        .reset             ( reset        ),
        .enable            ( enable       ),
        .cs                ( cs           ),
        .wr                ( wr           ),
        .rd                ( rd           ),
        .byte_lanes        ( 1'b1         ),
        .addr              ( addr         ),
        .wdata             ( wdata        ),
        .rdata             ( rdata        ),
        .int_in_cs         (              ),
        .int_in_dec        (              ),
        .irq_enable_cs     (              ),
        .irq_enable_dec    (              ),
        .irq_enable_wr_0   (              ),
        .irq_act_cs        (              ),
        .irq_act_dec       (              ),
        .irq_vec_cs        (              ),
        .irq_vec_dec       (              ),
        .int_in_rdata      ( int_in       ),
        .irq_act_rdata     ( irq_act      ),
        .irq_vec_rdata     ( vector       ),
        .irq_enable        ( irq_enable   ),
        .next_irq_enable   ( irq_enable   ),
        .irq_enable_rdata  ( irq_enable   )
);
 
 
 
 
 
 
always@(posedge clk)
if (reset)
   begin
   irq_act     <= 8'h00;
   irq_out     <= 1'b0;
   end
else
  begin
   irq_act     <=  irq_enable & int_in;
   irq_out     <=  | irq_act;
   end
 
 
 
always@(posedge clk)
if (reset)
                   vector  <= VEC_NONE;
 
else
if(irq_act[0])     vector  <= VEC_00;
else
if(irq_act[1])     vector  <= VEC_01;
else
if(irq_act[2])     vector  <= VEC_02;
else
if(irq_act[3])     vector  <= VEC_03;
else
if(irq_act[4])     vector  <= VEC_04;
else
if(irq_act[5])     vector  <= VEC_05;
else
if(irq_act[6])     vector  <= VEC_06;
else
if(irq_act[7])     vector  <= VEC_07;
else
                   vector  <= VEC_NONE;
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`wire [7:0] irq_enable;`
3			`reg [7:0] irq_act;`
4
5
6
7
8
9			`VARIANT`MB
10			`#(.IRQ_ENABLE_RST(IRQ_MODE))`
11			`vic_micro_reg`
12			`(`
13			`.clk ( clk ),`
14			`.reset ( reset ),`
15			`.enable ( enable ),`
16			`.cs ( cs ),`
17			`.wr ( wr ),`
18			`.rd ( rd ),`
19			`.byte_lanes ( 1'b1 ),`
20			`.addr ( addr ),`
21			`.wdata ( wdata ),`
22			`.rdata ( rdata ),`
23			`.int_in_cs ( ),`
24			`.int_in_dec ( ),`
25			`.irq_enable_cs ( ),`
26			`.irq_enable_dec ( ),`
27			`.irq_enable_wr_0 ( ),`
28			`.irq_act_cs ( ),`
29			`.irq_act_dec ( ),`
30			`.irq_vec_cs ( ),`
31			`.irq_vec_dec ( ),`
32			`.int_in_rdata ( int_in ),`
33			`.irq_act_rdata ( irq_act ),`
34			`.irq_vec_rdata ( vector ),`
35			`.irq_enable ( irq_enable ),`
36			`.next_irq_enable ( irq_enable ),`
37			`.irq_enable_rdata ( irq_enable )`
38			`);`
39
40
41
42
43
44
45			`always@(posedge clk)`
46			`if (reset)`
47			`begin`
48			`irq_act <= 8'h00;`
49			`irq_out <= 1'b0;`
50			`end`
51			`else`
52			`begin`
53			`irq_act <= irq_enable & int_in;`
54			`irq_out <= \| irq_act;`
55			`end`
56
57
58
59			`always@(posedge clk)`
60			`if (reset)`
61			`vector <= VEC_NONE;`
62
63			`else`
64			`if(irq_act[0]) vector <= VEC_00;`
65			`else`
66			`if(irq_act[1]) vector <= VEC_01;`
67			`else`
68			`if(irq_act[2]) vector <= VEC_02;`
69			`else`
70			`if(irq_act[3]) vector <= VEC_03;`
71			`else`
72			`if(irq_act[4]) vector <= VEC_04;`
73			`else`
74			`if(irq_act[5]) vector <= VEC_05;`
75			`else`
76			`if(irq_act[6]) vector <= VEC_06;`
77			`else`
78			`if(irq_act[7]) vector <= VEC_07;`
79			`else`
80			`vector <= VEC_NONE;`
81
82
83

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [verilog/] [top.body] - Blame information for rev 131