URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [xml/] [io_vic_def.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_vic
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 

 
 
 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      io_vic_def
    
  

 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_vic_def
        verilogSourcemodule
      
 
 
    
        mb
        ../verilog/io_vic_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_vic"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

IRQ_MODE8'h00
VEC_008'he0
VEC_018'he2
VEC_028'he4
VEC_038'he6
VEC_048'he8
VEC_058'hea
VEC_068'hec
VEC_078'hee
VEC_NONE8'h00

 
 

 
 
enable
wire
in

 
 
int_in
wire
in
70

 
irq_out
reg
out

 
vector
reg
out
70

 


 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   int_in
   0x0
   8
   read-only
  
 
 
   irq_enable
   0x2
   8
   read-write
  
 
 
 
   irq_act
   0x6
   8
   read-only
  
 
 
   irq_vec
   0x8
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [xml/] [io_vic_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_vic`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80			`rdata`
81
82			`rdata`
83			`wire`
84			`70`
85
86
87
88
89			`addr`
90
91			`addr`
92			`30`
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141	133	jt_eaton
142	131	jt_eaton
143			`gen_registers`
144	133	jt_eaton	`102.1`
145	131	jt_eaton	`common`
146			`none`
147			`./tools/regtool/gen_registers`
148
149
150			`bus_intf`
151			`mb`
152
153
154			`dest_dir`
155			`../verilog`
156
157
158
159
160
161
162			`gen_verilog`
163			`104.0`
164			`none`
165			`common`
166			`./tools/verilog/gen_verilog`
167
168
169			`destination`
170	134	jt_eaton	`io_vic_def`
171	131	jt_eaton
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186			`fs-common`
187
188
189
190			`../verilog/top.body`
191			`verilogSourcefragment`
192
193
194
195
196
197
198
199			`fs-sim`
200
201
202
203			`../verilog/copyright.v`
204			`verilogSourceinclude`
205
206
207
208
209	134	jt_eaton	`../verilog/common/io_vic_def`
210	131	jt_eaton	`verilogSourcemodule`
211
212
213
214
215			`mb`
216			`../verilog/io_vic_def_mb`
217			`verilogSourcemodule`
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238			`Hierarchical`
239
240
241			`spirit:library="io"`
242			`spirit:name="io_vic"`
243			`spirit:version="def.design"/>`
244
245
246
247
248			`verilog`
249
250
251			`spirit:library="Testbench"`
252			`spirit:name="toolflow"`
253			`spirit:version="verilog"/>`
254
255
256
257
258
259
260
261
262			`commoncommon`
263
264			`Verilog`
265
266
267			`fs-common`
268
269
270
271
272			`sim:Simulation:`
273
274			`Verilog`
275
276
277			`fs-sim`
278
279
280
281
282			`syn:Synthesis:`
283
284			`Verilog`
285
286
287			`fs-sim`
288
289
290
291
292
293
294			`doc`
295
296
297			`spirit:library="Testbench"`
298			`spirit:name="toolflow"`
299			`spirit:version="documentation"/>`
300
301			`:Documentation:`
302			`Verilog`
303
304
305
306
307
308
309
310
311			`IRQ_MODE8'h00`
312			`VEC_008'he0`
313			`VEC_018'he2`
314			`VEC_028'he4`
315			`VEC_038'he6`
316			`VEC_048'he8`
317			`VEC_058'hea`
318			`VEC_068'hec`
319			`VEC_078'hee`
320			`VEC_NONE8'h00`
321
322
323
324
325
326
327			`enable`
328			`wire`
329			`in`
330
331
332
333			`int_in`
334			`wire`
335			`in`
336			`70`
337
338
339			`irq_out`
340			`reg`
341			`out`
342
343
344			`vector`
345			`reg`
346			`out`
347			`70`
348
349
350
351
352
353
354
355
356
357			`mb`
358			`8`
359
360			`mb`
361			`0x00`
362
363
364			`mb_microbus`
365			`0x10`
366			`8`
367
368
369
370			`int_in`
371			`0x0`
372			`8`
373			`read-only`
374
375
376
377			`irq_enable`
378			`0x2`
379			`8`
380			`read-write`
381
382
383
384
385			`irq_act`
386			`0x6`
387			`8`
388			`read-only`
389
390
391
392			`irq_vec`
393			`0x8`
394			`8`
395			`read-only`
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411