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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [sim/] [testbenches/] [xml/] [io_vic_def_duth.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
io
io_vic
def_duth.design

 

addr



 

clk



 

cs



 

enable



 

int_in



 

irq_out



 

rd



 

rdata



 

reset



 

vector



 

wdata



 

wr



 
 


 

dut







Line No.	Rev	Author	Line
1	133	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	133	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`io`
17			`io_vic`
18			`def_duth.design`
19
20	133	jt_eaton
21	135	jt_eaton
22			`addr`
23
24
25
26	133	jt_eaton
27	135	jt_eaton
28			`clk`
29
30
31
32	133	jt_eaton
33	135	jt_eaton
34			`cs`
35
36
37
38	133	jt_eaton
39	135	jt_eaton
40			`enable`
41
42
43
44	133	jt_eaton
45	135	jt_eaton
46			`int_in`
47
48
49
50	133	jt_eaton
51	135	jt_eaton
52			`irq_out`
53
54
55
56	133	jt_eaton
57	135	jt_eaton
58			`rd`
59
60
61
62	133	jt_eaton
63	135	jt_eaton
64			`rdata`
65
66
67
68	133	jt_eaton
69	135	jt_eaton
70			`reset`
71
72
73
74	133	jt_eaton
75	135	jt_eaton
76			`vector`
77
78
79
80	133	jt_eaton
81	135	jt_eaton
82			`wdata`
83
84
85
86	133	jt_eaton
87	135	jt_eaton
88			`wr`
89
90
91
92	133	jt_eaton
93
94	135	jt_eaton
95
96	133	jt_eaton
97	135	jt_eaton
98			`dut`
99
100
101
102
103
104

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [sim/] [testbenches/] [xml/] [io_vic_def_duth.design.xml] - Blame information for rev 135