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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [sim/] [testbenches/] [xml/] [io_vic_def_lint.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_vic
def_lint
 
 
 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 

  gen_design
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  

 

 
 
 
 
 

 
       
 
              
              Dut
              
              
                                   spirit:library="io"
                                   spirit:name="io_vic"
                                   spirit:version="def_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
      
 
 
 

 
 
 
 
 
 
  
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/io_vic_def_lint
        verilogSource
        module
      
 
 
    
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_vic`
40			`def_lint`
41
42
43
44
45	133	jt_eaton
46	131	jt_eaton
47	133	jt_eaton
48			`elab_verilog`
49			`102.1`
50			`none`
51			`:Simulation:`
52			`>`
53			`./tools/verilog/elab_verilog`
54
55
56			`configuration`
57			`default`
58
59
60			`dest_dir`
61			`io_ports`
62
63
64
65	131	jt_eaton
66	133	jt_eaton
67			`gen_design`
68			`102.1`
69			`none`
70			`:Simulation:`
71			`>`
72			`./tools/verilog/gen_design`
73
74
75			`dest_dir`
76			`io_ports`
77
78
79
80	131	jt_eaton
81	133	jt_eaton
82	131	jt_eaton
83
84	133	jt_eaton
85
86
87	131	jt_eaton
88
89
90
91
92			`Dut`
93
94
95			`spirit:library="io"`
96			`spirit:name="io_vic"`
97			`spirit:version="def_dut.params"/>`
98
99
100
101
102
103			`lint`
104			`:Lint:`
105			`Verilog`
106			`fs-lint`
107
108
109
110
111			`rtl_check`
112
113
114			`spirit:library="Testbench"`
115			`spirit:name="toolflow"`
116			`spirit:version="rtl_check"/>`
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136			`fs-lint`
137
138
139
140			`../verilog/lint/io_vic_def_lint`
141			`verilogSource`
142			`module`
143
144
145
146
147
148
149
150
151
152
153
154

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [sim/] [testbenches/] [xml/] [io_vic_def_lint.xml] - Blame information for rev 133