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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sch/] [micro_bus_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 2900 300 1 0 0 in_port_vector.sym
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{
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T 2900 300 5 10 1 1 0 6 1 1
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refdes=wdata_in[7:0]
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}
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C 2900 700 1 0 0 in_port_vector.sym
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{
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T 2900 700 5 10 1 1 0 6 1 1
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refdes=sh_prog_rom_mem_rdata[15:0]
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}
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C 2900 1100 1 0 0 in_port_vector.sym
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{
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T 2900 1100 5 10 1 1 0 6 1 1
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refdes=prog_rom_mem_rdata[15:0]
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}
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C 2900 1500 1 0 0 in_port_vector.sym
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{
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T 2900 1500 5 10 1 1 0 6 1 1
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refdes=mem_wait[1:0]
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}
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C 2900 1900 1 0 0 in_port_vector.sym
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{
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T 2900 1900 5 10 1 1 0 6 1 1
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refdes=mem_rdata[15:0]
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}
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C 2900 2300 1 0 0 in_port_vector.sym
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{
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T 2900 2300 5 10 1 1 0 6 1 1
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refdes=io_reg_rdata[15:0]
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}
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C 2900 2700 1 0 0 in_port_vector.sym
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{
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T 2900 2700 5 10 1 1 0 6 1 1
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refdes=ext_mem_rdata[15:0]
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}
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C 2900 3100 1 0 0 in_port_vector.sym
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{
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T 2900 3100 5 10 1 1 0 6 1 1
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refdes=data_rdata[15:0]
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}
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C 2900 3500 1 0 0 in_port_vector.sym
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{
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T 2900 3500 5 10 1 1 0 6 1 1
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refdes=addr_in[15:0]
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}
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C 2900 3900 1 0 0 in_port.sym
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{
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T 2900 3900 5 10 1 1 0 6 1 1
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refdes=wr_in
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}
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C 2900 4300 1 0 0 in_port.sym
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{
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T 2900 4300 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 2900 4700 1 0 0 in_port.sym
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{
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T 2900 4700 5 10 1 1 0 6 1 1
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refdes=rd_in
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}
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C 2900 5100 1 0 0 in_port.sym
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{
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T 2900 5100 5 10 1 1 0 6 1 1
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refdes=io_reg_wait
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}
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C 2900 5500 1 0 0 in_port.sym
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{
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T 2900 5500 5 10 1 1 0 6 1 1
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refdes=ext_mem_wait
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}
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C 2900 5900 1 0 0 in_port.sym
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{
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T 2900 5900 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 6900 300  1 0  0 out_port_vector.sym
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{
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T 7900 300 5  10 1 1 0 0 1 1
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refdes=sh_prog_rom_mem_wdata[15:0]
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}
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C 6900 700  1 0  0 out_port_vector.sym
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{
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T 7900 700 5  10 1 1 0 0 1 1
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refdes=sh_prog_rom_mem_addr[11:0]
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}
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C 6900 1100  1 0  0 out_port_vector.sym
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{
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T 7900 1100 5  10 1 1 0 0 1 1
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refdes=rdata_out[15:0]
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}
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C 6900 1500  1 0  0 out_port_vector.sym
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{
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T 7900 1500 5  10 1 1 0 0 1 1
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refdes=prog_rom_mem_wdata[15:0]
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}
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C 6900 1900  1 0  0 out_port_vector.sym
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{
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T 7900 1900 5  10 1 1 0 0 1 1
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refdes=prog_rom_mem_addr[11:0]
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}
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C 6900 2300  1 0  0 out_port_vector.sym
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{
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T 7900 2300 5  10 1 1 0 0 1 1
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refdes=mem_wdata[15:0]
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}
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C 6900 2700  1 0  0 out_port_vector.sym
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{
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T 7900 2700 5  10 1 1 0 0 1 1
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refdes=mem_addr[15:0]
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}
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C 6900 3100  1 0  0 out_port_vector.sym
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{
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T 7900 3100 5  10 1 1 0 0 1 1
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refdes=io_reg_wdata[7:0]
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}
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C 6900 3500  1 0  0 out_port_vector.sym
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{
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T 7900 3500 5  10 1 1 0 0 1 1
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refdes=io_reg_addr[7:0]
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}
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C 6900 3900  1 0  0 out_port_vector.sym
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{
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T 7900 3900 5  10 1 1 0 0 1 1
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refdes=ext_mem_wdata[15:0]
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}
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C 6900 4300  1 0  0 out_port_vector.sym
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{
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T 7900 4300 5  10 1 1 0 0 1 1
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refdes=ext_mem_addr[13:0]
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}
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C 6900 4700  1 0  0 out_port_vector.sym
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{
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T 7900 4700 5  10 1 1 0 0 1 1
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refdes=data_wdata[15:0]
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}
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C 6900 5100  1 0  0 out_port_vector.sym
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{
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T 7900 5100 5  10 1 1 0 0 1 1
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refdes=data_be[1:0]
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}
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C 6900 5500  1 0  0 out_port_vector.sym
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{
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T 7900 5500 5  10 1 1 0 0 1 1
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refdes=data_addr[11:1]
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}
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C 6900 5900  1 0 0 out_port.sym
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{
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T 7900 5900 5  10 1 1 0 0 1 1
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refdes=sh_prog_rom_mem_wr
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}
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C 6900 6300  1 0 0 out_port.sym
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{
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T 7900 6300 5  10 1 1 0 0 1 1
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refdes=sh_prog_rom_mem_rd
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}
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C 6900 6700  1 0 0 out_port.sym
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{
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T 7900 6700 5  10 1 1 0 0 1 1
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refdes=sh_prog_rom_mem_cs
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}
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C 6900 7100  1 0 0 out_port.sym
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{
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T 7900 7100 5  10 1 1 0 0 1 1
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refdes=prog_rom_mem_wr
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}
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C 6900 7500  1 0 0 out_port.sym
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{
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T 7900 7500 5  10 1 1 0 0 1 1
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refdes=prog_rom_mem_rd
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}
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C 6900 7900  1 0 0 out_port.sym
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{
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T 7900 7900 5  10 1 1 0 0 1 1
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refdes=prog_rom_mem_cs
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}
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C 6900 8300  1 0 0 out_port.sym
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{
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T 7900 8300 5  10 1 1 0 0 1 1
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refdes=mem_wr
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}
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C 6900 8700  1 0 0 out_port.sym
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{
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T 7900 8700 5  10 1 1 0 0 1 1
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refdes=mem_rd
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}
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C 6900 9100  1 0 0 out_port.sym
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{
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T 7900 9100 5  10 1 1 0 0 1 1
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refdes=mem_cs
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}
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C 6900 9500  1 0 0 out_port.sym
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{
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T 7900 9500 5  10 1 1 0 0 1 1
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refdes=io_reg_wr
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}
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C 6900 9900  1 0 0 out_port.sym
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{
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T 7900 9900 5  10 1 1 0 0 1 1
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refdes=io_reg_rd
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}
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C 6900 10300  1 0 0 out_port.sym
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{
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T 7900 10300 5  10 1 1 0 0 1 1
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refdes=io_reg_cs
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}
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C 6900 10700  1 0 0 out_port.sym
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{
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T 7900 10700 5  10 1 1 0 0 1 1
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refdes=ext_mem_wr
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}
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C 6900 11100  1 0 0 out_port.sym
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{
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T 7900 11100 5  10 1 1 0 0 1 1
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refdes=ext_mem_rd
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}
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C 6900 11500  1 0 0 out_port.sym
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{
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T 7900 11500 5  10 1 1 0 0 1 1
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refdes=ext_mem_cs
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}
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C 6900 11900  1 0 0 out_port.sym
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{
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T 7900 11900 5  10 1 1 0 0 1 1
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refdes=enable
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}
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C 6900 12300  1 0 0 out_port.sym
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{
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T 7900 12300 5  10 1 1 0 0 1 1
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refdes=data_wr
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}
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C 6900 12700  1 0 0 out_port.sym
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{
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T 7900 12700 5  10 1 1 0 0 1 1
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refdes=data_rd
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}
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C 6900 13100  1 0 0 out_port.sym
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{
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T 7900 13100 5  10 1 1 0 0 1 1
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refdes=data_cs
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}

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