OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sch/] [uart_tx.sch] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
C 2600 300 1 0 0 in_port_vector.sym
3 
{
4 
T 2600 300 5 10 1 1 0 6 1 1
5 
refdes=txd_data_in[SIZE-1:0]
6 
}
7 
C 2600 700 1 0 0 in_port_vector.sym
8 
{
9 
T 2600 700 5 10 1 1 0 6 1 1
10 
refdes=divider_in[DIV_SIZE-1:0]
11 
}
12 
C 2600 1100 1 0 0 in_port.sym
13 
{
14 
T 2600 1100 5 10 1 1 0 6 1 1
15 
refdes=txd_parity
16 
}
17 
C 2600 1500 1 0 0 in_port.sym
18 
{
19 
T 2600 1500 5 10 1 1 0 6 1 1
20 
refdes=txd_load
21 
}
22 
C 2600 1900 1 0 0 in_port.sym
23 
{
24 
T 2600 1900 5 10 1 1 0 6 1 1
25 
refdes=txd_force_parity
26 
}
27 
C 2600 2300 1 0 0 in_port.sym
28 
{
29 
T 2600 2300 5 10 1 1 0 6 1 1
30 
refdes=txd_break
31 
}
32 
C 2600 2700 1 0 0 in_port.sym
33 
{
34 
T 2600 2700 5 10 1 1 0 6 1 1
35 
refdes=rxd_parity
36 
}
37 
C 2600 3100 1 0 0 in_port.sym
38 
{
39 
T 2600 3100 5 10 1 1 0 6 1 1
40 
refdes=rxd_pad_in
41 
}
42 
C 2600 3500 1 0 0 in_port.sym
43 
{
44 
T 2600 3500 5 10 1 1 0 6 1 1
45 
refdes=rxd_force_parity
46 
}
47 
C 2600 3900 1 0 0 in_port.sym
48 
{
49 
T 2600 3900 5 10 1 1 0 6 1 1
50 
refdes=rxd_data_avail_stb
51 
}
52 
C 2600 4300 1 0 0 in_port.sym
53 
{
54 
T 2600 4300 5 10 1 1 0 6 1 1
55 
refdes=rts_in
56 
}
57 
C 2600 4700 1 0 0 in_port.sym
58 
{
59 
T 2600 4700 5 10 1 1 0 6 1 1
60 
refdes=reset
61 
}
62 
C 2600 5100 1 0 0 in_port.sym
63 
{
64 
T 2600 5100 5 10 1 1 0 6 1 1
65 
refdes=parity_enable
66 
}
67 
C 2600 5500 1 0 0 in_port.sym
68 
{
69 
T 2600 5500 5 10 1 1 0 6 1 1
70 
refdes=cts_pad_in
71 
}
72 
C 2600 5900 1 0 0 in_port.sym
73 
{
74 
T 2600 5900 5 10 1 1 0 6 1 1
75 
refdes=clk
76 
}
77 
C 6100 300  1 0  0 out_port_vector.sym
78 
{
79 
T 7100 300 5  10 1 1 0 0 1 1
80 
refdes=rxd_data_out[SIZE-1:0]
81 
}
82 
C 6100 700  1 0 0 out_port.sym
83 
{
84 
T 7100 700 5  10 1 1 0 0 1 1
85 
refdes=txd_pad_out
86 
}
87 
C 6100 1100  1 0 0 out_port.sym
88 
{
89 
T 7100 1100 5  10 1 1 0 0 1 1
90 
refdes=txd_buffer_empty
91 
}
92 
C 6100 1500  1 0 0 out_port.sym
93 
{
94 
T 7100 1500 5  10 1 1 0 0 1 1
95 
refdes=rxd_stop_error
96 
}
97 
C 6100 1900  1 0 0 out_port.sym
98 
{
99 
T 7100 1900 5  10 1 1 0 0 1 1
100 
refdes=rxd_parity_error
101 
}
102 
C 6100 2300  1 0 0 out_port.sym
103 
{
104 
T 7100 2300 5  10 1 1 0 0 1 1
105 
refdes=rxd_data_avail
106 
}
107 
C 6100 2700  1 0 0 out_port.sym
108 
{
109 
T 7100 2700 5  10 1 1 0 0 1 1
110 
refdes=rts_pad_out
111 
}
112 
C 6100 3100  1 0 0 out_port.sym
113 
{
114 
T 7100 3100 5  10 1 1 0 0 1 1
115 
refdes=cts_out
116 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.