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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sym/] [uart_def.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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B 300 0  5000 3300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 400 3450   5 10 1 1 0 0 1 1
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device=uart_def
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T 400 3650 5 10 1 1 0 0 1 1
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refdes=U?
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T 400 3800    0 10 0 1 0 0 1 1
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vendor=opencores.org
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T 400 3800    0 10 0 1 0 0 1 1
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library=logic
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T 400 3800    0 10 0 1 0 0 1 1
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component=uart
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T 400 3800    0 10 0 1 0 0 1 1
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version=def
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P 300 200 0 200 10 1 1
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{
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T 400 200 5 10 1 1 0 1 1 1
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pinnumber=txd_data_in[SIZE-1:0]
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T 400 200 5 10 0 1 0 1 1 1
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pinseq=1
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}
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P 300 400 0 400 10 1 1
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{
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T 400 400 5 10 1 1 0 1 1 1
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pinnumber=divider_in[DIV_SIZE-1:0]
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T 400 400 5 10 0 1 0 1 1 1
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pinseq=2
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}
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P 300 600 0 600 4 0 1
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{
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T 400 600 5 10 1 1 0 1 1 1
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pinnumber=txd_parity
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T 400 600 5 10 0 1 0 1 1 1
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pinseq=3
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}
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P 300 800 0 800 4 0 1
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{
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T 400 800 5 10 1 1 0 1 1 1
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pinnumber=txd_load
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T 400 800 5 10 0 1 0 1 1 1
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pinseq=4
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}
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P 300 1000 0 1000 4 0 1
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{
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T 400 1000 5 10 1 1 0 1 1 1
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pinnumber=txd_force_parity
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T 400 1000 5 10 0 1 0 1 1 1
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pinseq=5
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}
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P 300 1200 0 1200 4 0 1
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{
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T 400 1200 5 10 1 1 0 1 1 1
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pinnumber=txd_break
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T 400 1200 5 10 0 1 0 1 1 1
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pinseq=6
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}
57 
P 300 1400 0 1400 4 0 1
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{
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T 400 1400 5 10 1 1 0 1 1 1
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pinnumber=rxd_parity
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T 400 1400 5 10 0 1 0 1 1 1
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pinseq=7
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}
64 
P 300 1600 0 1600 4 0 1
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{
66 
T 400 1600 5 10 1 1 0 1 1 1
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pinnumber=rxd_pad_in
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T 400 1600 5 10 0 1 0 1 1 1
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pinseq=8
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}
71 
P 300 1800 0 1800 4 0 1
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{
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T 400 1800 5 10 1 1 0 1 1 1
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pinnumber=rxd_force_parity
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T 400 1800 5 10 0 1 0 1 1 1
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pinseq=9
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}
78 
P 300 2000 0 2000 4 0 1
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{
80 
T 400 2000 5 10 1 1 0 1 1 1
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pinnumber=rxd_data_avail_stb
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T 400 2000 5 10 0 1 0 1 1 1
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pinseq=10
84 
}
85 
P 300 2200 0 2200 4 0 1
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{
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T 400 2200 5 10 1 1 0 1 1 1
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pinnumber=rts_in
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T 400 2200 5 10 0 1 0 1 1 1
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pinseq=11
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}
92 
P 300 2400 0 2400 4 0 1
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{
94 
T 400 2400 5 10 1 1 0 1 1 1
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pinnumber=reset
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T 400 2400 5 10 0 1 0 1 1 1
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pinseq=12
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}
99 
P 300 2600 0 2600 4 0 1
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{
101 
T 400 2600 5 10 1 1 0 1 1 1
102 
pinnumber=parity_enable
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T 400 2600 5 10 0 1 0 1 1 1
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pinseq=13
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}
106 
P 300 2800 0 2800 4 0 1
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{
108 
T 400 2800 5 10 1 1 0 1 1 1
109 
pinnumber=cts_pad_in
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T 400 2800 5 10 0 1 0 1 1 1
111 
pinseq=14
112 
}
113 
P 300 3000 0 3000 4 0 1
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{
115 
T 400 3000 5 10 1 1 0 1 1 1
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pinnumber=clk
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T 400 3000 5 10 0 1 0 1 1 1
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pinseq=15
119 
}
120 
P 5300 200 5600 200 10 1 1
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{
122 
T 5200 200 5  10 1 1 0 7 1 1
123 
pinnumber=rxd_data_out[SIZE-1:0]
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T 5200 200 5  10 0 1 0 7 1 1
125 
pinseq=16
126 
}
127 
P 5300 400 5600 400 4 0 1
128 
{
129 
T 5200 400 5  10 1 1 0 7 1 1
130 
pinnumber=txd_pad_out
131 
T 5300 400 5  10 0 1 0 7 1 1
132 
pinseq=17
133 
}
134 
P 5300 600 5600 600 4 0 1
135 
{
136 
T 5200 600 5  10 1 1 0 7 1 1
137 
pinnumber=txd_buffer_empty
138 
T 5300 600 5  10 0 1 0 7 1 1
139 
pinseq=18
140 
}
141 
P 5300 800 5600 800 4 0 1
142 
{
143 
T 5200 800 5  10 1 1 0 7 1 1
144 
pinnumber=rxd_stop_error
145 
T 5300 800 5  10 0 1 0 7 1 1
146 
pinseq=19
147 
}
148 
P 5300 1000 5600 1000 4 0 1
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{
150 
T 5200 1000 5  10 1 1 0 7 1 1
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pinnumber=rxd_parity_error
152 
T 5300 1000 5  10 0 1 0 7 1 1
153 
pinseq=20
154 
}
155 
P 5300 1200 5600 1200 4 0 1
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{
157 
T 5200 1200 5  10 1 1 0 7 1 1
158 
pinnumber=rxd_data_avail
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T 5300 1200 5  10 0 1 0 7 1 1
160 
pinseq=21
161 
}
162 
P 5300 1400 5600 1400 4 0 1
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{
164 
T 5200 1400 5  10 1 1 0 7 1 1
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pinnumber=rts_pad_out
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T 5300 1400 5  10 0 1 0 7 1 1
167 
pinseq=22
168 
}
169 
P 5300 1600 5600 1600 4 0 1
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{
171 
T 5200 1600 5  10 1 1 0 7 1 1
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pinnumber=cts_out
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T 5300 1600 5  10 0 1 0 7 1 1
174 
pinseq=23
175 
}

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