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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
disp_io
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 
 

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 
 
 
 

       
 
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
 
PosD
wire
in
150

 
PosL
wire
in
70

 
PosB
reg
out
30

 
PosS
reg
out
70

 
btn_pad_in
wire
in
30

 
sw_pad_in
wire
in
70

 
led_pad_out
reg
out
70

 
seg_pad_out
reg
out
60

 
dp_pad_out
reg
out

 
an_pad_out
reg
out
30

 

 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`disp_io`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84			`gen_verilog`
85			`104.0`
86			`none`
87			`common`
88			`./tools/verilog/gen_verilog`
89
90
91			`destination`
92			`top`
93
94
95			`dest_dir`
96			`../verilog`
97
98
99
100
101
102
103
104
105
106
107
108
109
110			`fs-common`
111
112
113
114			`../verilog/top.body`
115			`verilogSourcefragment`
116
117
118
119
120
121
122			`fs-sim`
123
124
125
126			`../verilog/copyright.v`
127			`verilogSourceinclude`
128
129
130
131
132			`../verilog/common/top`
133			`verilogSourcemodule`
134
135
136
137
138
139
140
141
142
143			`fs-syn`
144
145
146
147			`../verilog/copyright.v`
148			`verilogSourceinclude`
149
150
151
152
153			`../verilog/common/top`
154			`verilogSourcemodule`
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175			`Hierarchical`
176
177
178			`spirit:library="logic"`
179			`spirit:name="disp_io"`
180			`spirit:version="def.design"/>`
181
182
183
184
185			`verilog`
186
187
188			`spirit:library="Testbench"`
189			`spirit:name="toolflow"`
190			`spirit:version="verilog"/>`
191
192
193
194
195
196
197
198
199			`commoncommon`
200
201			`Verilog`
202
203
204			`fs-common`
205
206
207
208
209
210			`sim:Simulation:`
211
212			`Verilog`
213
214
215			`fs-sim`
216
217
218
219
220
221			`syn:Synthesis:`
222
223			`Verilog`
224
225
226			`fs-syn`
227
228
229
230
231
232
233
234
235
236			`doc`
237
238
239			`spirit:library="Testbench"`
240			`spirit:name="toolflow"`
241			`spirit:version="documentation"/>`
242
243			`:Documentation:`
244			`Verilog`
245
246
247
248
249
250
251
252
253
254
255
256			`PosD`
257			`wire`
258			`in`
259			`150`
260
261
262			`PosL`
263			`wire`
264			`in`
265			`70`
266
267
268			`PosB`
269			`reg`
270			`out`
271			`30`
272
273
274			`PosS`
275			`reg`
276			`out`
277			`70`
278
279
280			`btn_pad_in`
281			`wire`
282			`in`
283			`30`
284
285
286			`sw_pad_in`
287			`wire`
288			`in`
289			`70`
290
291
292			`led_pad_out`
293			`reg`
294			`out`
295			`70`
296
297
298			`seg_pad_out`
299			`reg`
300			`out`
301			`60`
302
303
304			`dp_pad_out`
305			`reg`
306			`out`
307
308
309			`an_pad_out`
310			`reg`
311			`out`
312			`30`
313
314
315
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325