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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
disp_io
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 
 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 
 
 
 

       
 
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
 
PosD
wire
in
150

 
PosL
wire
in
70

 
PosB
reg
out
30

 
PosS
reg
out
70

 
btn_pad_in
wire
in
30

 
sw_pad_in
wire
in
70

 
led_pad_out
reg
out
70

 
seg_pad_out
reg
out
60

 
dp_pad_out
reg
out

 
an_pad_out
reg
out
30

 

 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`disp_io`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80	133	jt_eaton
81			`elab_verilog`
82			`102.1`
83			`none`
84			`:Simulation:`
85			`./tools/verilog/elab_verilog`
86
87
88			`dest_dir`
89			`io_ports`
90
91
92
93	131	jt_eaton
94
95
96	133	jt_eaton
97
98	131	jt_eaton
99			`gen_verilog`
100			`104.0`
101			`none`
102			`common`
103			`./tools/verilog/gen_verilog`
104
105
106			`destination`
107			`top`
108
109
110			`dest_dir`
111			`../verilog`
112
113
114
115
116
117
118
119
120
121
122
123
124
125			`fs-common`
126
127
128
129			`../verilog/top.body`
130			`verilogSourcefragment`
131
132
133
134
135
136
137			`fs-sim`
138
139
140
141			`../verilog/copyright.v`
142			`verilogSourceinclude`
143
144
145
146
147			`../verilog/common/top`
148			`verilogSourcemodule`
149
150
151
152
153
154
155
156
157
158			`fs-syn`
159
160
161
162			`../verilog/copyright.v`
163			`verilogSourceinclude`
164
165
166
167
168			`../verilog/common/top`
169			`verilogSourcemodule`
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190			`Hierarchical`
191
192
193			`spirit:library="logic"`
194			`spirit:name="disp_io"`
195			`spirit:version="def.design"/>`
196
197
198
199
200			`verilog`
201
202
203			`spirit:library="Testbench"`
204			`spirit:name="toolflow"`
205			`spirit:version="verilog"/>`
206
207
208
209
210
211
212
213
214			`commoncommon`
215
216			`Verilog`
217
218
219			`fs-common`
220
221
222
223
224
225			`sim:Simulation:`
226
227			`Verilog`
228
229
230			`fs-sim`
231
232
233
234
235
236			`syn:Synthesis:`
237
238			`Verilog`
239
240
241			`fs-syn`
242
243
244
245
246
247
248
249
250
251			`doc`
252
253
254			`spirit:library="Testbench"`
255			`spirit:name="toolflow"`
256			`spirit:version="documentation"/>`
257
258			`:Documentation:`
259			`Verilog`
260
261
262
263
264
265
266
267
268
269
270
271			`PosD`
272			`wire`
273			`in`
274			`150`
275
276
277			`PosL`
278			`wire`
279			`in`
280			`70`
281
282
283			`PosB`
284			`reg`
285			`out`
286			`30`
287
288
289			`PosS`
290			`reg`
291			`out`
292			`70`
293
294
295			`btn_pad_in`
296			`wire`
297			`in`
298			`30`
299
300
301			`sw_pad_in`
302			`wire`
303			`in`
304			`70`
305
306
307			`led_pad_out`
308			`reg`
309			`out`
310			`70`
311
312
313			`seg_pad_out`
314			`reg`
315			`out`
316			`60`
317
318
319			`dp_pad_out`
320			`reg`
321			`out`
322
323
324			`an_pad_out`
325			`reg`
326			`out`
327			`30`
328
329
330
331
332
333
334
335
336
337
338
339
340