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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
disp_io
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 
 

 
 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      disp_io_def
    
  

 
 
 

 
 
 
 
 

       
 
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
 
PosD
wire
in
150

 
PosL
wire
in
70

 
PosB
reg
out
30

 
PosS
reg
out
70

 
btn_pad_in
wire
in
30

 
sw_pad_in
wire
in
70

 
led_pad_out
reg
out
70

 
seg_pad_out
reg
out
60

 
dp_pad_out
reg
out

 
an_pad_out
reg
out
30

 

 

 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/disp_io_def
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/disp_io_def
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`disp_io`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
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81
82
83	133	jt_eaton
84	131	jt_eaton
85			`gen_verilog`
86			`104.0`
87			`none`
88			`common`
89			`./tools/verilog/gen_verilog`
90
91
92			`destination`
93	134	jt_eaton	`disp_io_def`
94	131	jt_eaton
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111			`Hierarchical`
112
113
114			`spirit:library="logic"`
115			`spirit:name="disp_io"`
116			`spirit:version="def.design"/>`
117
118
119
120
121			`verilog`
122
123
124			`spirit:library="Testbench"`
125			`spirit:name="toolflow"`
126			`spirit:version="verilog"/>`
127
128
129
130
131
132
133
134
135			`commoncommon`
136
137			`Verilog`
138
139
140			`fs-common`
141
142
143
144
145
146			`sim:Simulation:`
147
148			`Verilog`
149
150
151			`fs-sim`
152
153
154
155
156
157			`syn:Synthesis:`
158
159			`Verilog`
160
161
162			`fs-syn`
163
164
165
166
167
168
169
170
171
172			`doc`
173
174
175			`spirit:library="Testbench"`
176			`spirit:name="toolflow"`
177			`spirit:version="documentation"/>`
178
179			`:Documentation:`
180			`Verilog`
181
182
183
184
185
186
187
188
189
190
191
192			`PosD`
193			`wire`
194			`in`
195			`150`
196
197
198			`PosL`
199			`wire`
200			`in`
201			`70`
202
203
204			`PosB`
205			`reg`
206			`out`
207			`30`
208
209
210			`PosS`
211			`reg`
212			`out`
213			`70`
214
215
216			`btn_pad_in`
217			`wire`
218			`in`
219			`30`
220
221
222			`sw_pad_in`
223			`wire`
224			`in`
225			`70`
226
227
228			`led_pad_out`
229			`reg`
230			`out`
231			`70`
232
233
234			`seg_pad_out`
235			`reg`
236			`out`
237			`60`
238
239
240			`dp_pad_out`
241			`reg`
242			`out`
243
244
245			`an_pad_out`
246			`reg`
247			`out`
248			`30`
249
250
251
252
253
254
255
256
257	134	jt_eaton
258	131	jt_eaton
259
260	134	jt_eaton
261			`fs-common`
262	131	jt_eaton
263	134	jt_eaton
264
265			`../verilog/top.body`
266			`verilogSourcefragment`
267
268	131	jt_eaton
269	134	jt_eaton
270
271
272
273			`fs-sim`
274
275
276
277			`../verilog/copyright`
278			`verilogSourceinclude`
279
280
281
282
283			`../verilog/common/disp_io_def`
284			`verilogSourcemodule`
285
286
287
288
289
290
291
292
293
294			`fs-syn`
295
296
297
298			`../verilog/copyright`
299			`verilogSourceinclude`
300
301
302
303
304			`../verilog/common/disp_io_def`
305			`verilogSourcemodule`
306
307
308
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312
313
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321
322	131	jt_eaton