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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_jtag.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
disp_io
jtag  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 
 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      jtag.top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.jtag
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/jtag.top
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/jtag.top
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 
 
 
 

       
 
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="jtag.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
 
PosD
wire
in
150

 
PosL
wire
in
70

 
PosB
reg
out
30

 
PosS
reg
out
70

 
btn_pad_in
wire
in
30

 
sw_pad_in
wire
in
70

 
led_pad_out
reg
out
70

 
seg_pad_out
reg
out
60

 
dp_pad_out
reg
out

 
an_pad_out
reg
out
30

 

 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_jtag.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	133	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`disp_io`
40			`jtag default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81			`elab_verilog`
82			`102.1`
83			`none`
84			`:Simulation:`
85			`./tools/verilog/elab_verilog`
86
87
88			`dest_dir`
89			`io_ports`
90
91
92
93
94
95
96
97
98			`gen_verilog`
99			`104.0`
100			`none`
101			`common`
102			`./tools/verilog/gen_verilog`
103
104
105			`destination`
106			`jtag.top`
107
108
109			`dest_dir`
110			`../verilog`
111
112
113
114
115
116
117
118
119
120
121
122
123
124			`fs-common`
125
126
127
128			`../verilog/top.jtag`
129			`verilogSourcefragment`
130
131
132
133
134
135
136			`fs-sim`
137
138
139
140			`../verilog/copyright.v`
141			`verilogSourceinclude`
142
143
144
145
146			`../verilog/common/jtag.top`
147			`verilogSourcemodule`
148
149
150
151
152
153
154
155
156
157			`fs-syn`
158
159
160
161			`../verilog/copyright.v`
162			`verilogSourceinclude`
163
164
165
166
167			`../verilog/common/jtag.top`
168			`verilogSourcemodule`
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189			`Hierarchical`
190
191
192			`spirit:library="logic"`
193			`spirit:name="disp_io"`
194			`spirit:version="jtag.design"/>`
195
196
197
198
199			`verilog`
200
201
202			`spirit:library="Testbench"`
203			`spirit:name="toolflow"`
204			`spirit:version="verilog"/>`
205
206
207
208
209
210
211
212
213			`commoncommon`
214
215			`Verilog`
216
217
218			`fs-common`
219
220
221
222
223
224			`sim:Simulation:`
225
226			`Verilog`
227
228
229			`fs-sim`
230
231
232
233
234
235			`syn:Synthesis:`
236
237			`Verilog`
238
239
240			`fs-syn`
241
242
243
244
245
246
247
248
249
250			`doc`
251
252
253			`spirit:library="Testbench"`
254			`spirit:name="toolflow"`
255			`spirit:version="documentation"/>`
256
257			`:Documentation:`
258			`Verilog`
259
260
261
262
263
264
265
266
267
268
269
270			`PosD`
271			`wire`
272			`in`
273			`150`
274
275
276			`PosL`
277			`wire`
278			`in`
279			`70`
280
281
282			`PosB`
283			`reg`
284			`out`
285			`30`
286
287
288			`PosS`
289			`reg`
290			`out`
291			`70`
292
293
294			`btn_pad_in`
295			`wire`
296			`in`
297			`30`
298
299
300			`sw_pad_in`
301			`wire`
302			`in`
303			`70`
304
305
306			`led_pad_out`
307			`reg`
308			`out`
309			`70`
310
311
312			`seg_pad_out`
313			`reg`
314			`out`
315			`60`
316
317
318			`dp_pad_out`
319			`reg`
320			`out`
321
322
323			`an_pad_out`
324			`reg`
325			`out`
326			`30`
327
328
329
330
331
332
333
334
335
336
337
338
339