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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_jtag.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
disp_io
jtag  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 
 

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      disp_io_jtag
    
  

 
 
 

 
 
 
 
 
 
 

       
 
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="jtag.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
 
PosD
wire
in
150

 
PosL
wire
in
70

 
PosB
reg
out
30

 
PosS
reg
out
70

 
btn_pad_in
wire
in
30

 
sw_pad_in
wire
in
70

 
led_pad_out
reg
out
70

 
seg_pad_out
reg
out
60

 
dp_pad_out
reg
out

 
an_pad_out
reg
out
30

 

 

 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.jtag
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/disp_io_jtag
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/disp_io_jtag
        verilogSourcemodule
      
 
    
 
 
  
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_jtag.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	jt_eaton
2	133	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`disp_io`
40			`jtag default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82			`gen_verilog`
83			`104.0`
84			`none`
85			`common`
86			`./tools/verilog/gen_verilog`
87
88
89			`destination`
90	134	jt_eaton	`disp_io_jtag`
91	133	jt_eaton
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110			`Hierarchical`
111
112
113			`spirit:library="logic"`
114			`spirit:name="disp_io"`
115			`spirit:version="jtag.design"/>`
116
117
118
119
120			`verilog`
121
122
123			`spirit:library="Testbench"`
124			`spirit:name="toolflow"`
125			`spirit:version="verilog"/>`
126
127
128
129
130
131
132
133
134			`commoncommon`
135
136			`Verilog`
137
138
139			`fs-common`
140
141
142
143
144
145			`sim:Simulation:`
146
147			`Verilog`
148
149
150			`fs-sim`
151
152
153
154
155
156			`syn:Synthesis:`
157
158			`Verilog`
159
160
161			`fs-syn`
162
163
164
165
166
167
168
169
170
171			`doc`
172
173
174			`spirit:library="Testbench"`
175			`spirit:name="toolflow"`
176			`spirit:version="documentation"/>`
177
178			`:Documentation:`
179			`Verilog`
180
181
182
183
184
185
186
187
188
189
190
191			`PosD`
192			`wire`
193			`in`
194			`150`
195
196
197			`PosL`
198			`wire`
199			`in`
200			`70`
201
202
203			`PosB`
204			`reg`
205			`out`
206			`30`
207
208
209			`PosS`
210			`reg`
211			`out`
212			`70`
213
214
215			`btn_pad_in`
216			`wire`
217			`in`
218			`30`
219
220
221			`sw_pad_in`
222			`wire`
223			`in`
224			`70`
225
226
227			`led_pad_out`
228			`reg`
229			`out`
230			`70`
231
232
233			`seg_pad_out`
234			`reg`
235			`out`
236			`60`
237
238
239			`dp_pad_out`
240			`reg`
241			`out`
242
243
244			`an_pad_out`
245			`reg`
246			`out`
247			`30`
248
249
250
251
252
253
254
255
256	134	jt_eaton
257	133	jt_eaton
258
259	134	jt_eaton
260			`fs-common`
261	133	jt_eaton
262	134	jt_eaton
263
264			`../verilog/top.jtag`
265			`verilogSourcefragment`
266
267	133	jt_eaton
268	134	jt_eaton
269
270
271
272			`fs-sim`
273
274
275
276			`../verilog/copyright`
277			`verilogSourceinclude`
278
279
280
281
282			`../verilog/common/disp_io_jtag`
283			`verilogSourcemodule`
284
285
286
287
288
289
290
291
292
293			`fs-syn`
294
295
296
297			`../verilog/copyright`
298			`verilogSourceinclude`
299
300
301
302
303			`../verilog/common/disp_io_jtag`
304			`verilogSourcemodule`
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319	133	jt_eaton