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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [xml/] [disp_io_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
disp_io
def_tb
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 
 
 

 
 
 
 
 

 
       
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="def_dut.params"/>
             
              
 
 
 
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
      
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 

 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`disp_io`
40			`def_tb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57			`top.tb`
58
59
60			`dest_dir`
61			`../verilog`
62
63
64			`top`
65
66
67
68
69
70
71
72
73
74
75
76
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81
82
83
84			`Params`
85
86
87			`spirit:library="logic"`
88			`spirit:name="disp_io"`
89			`spirit:version="def_dut.params"/>`
90
91
92
93
94
95
96
97			`Bfm`
98
99			`spirit:library="logic"`
100			`spirit:name="disp_io"`
101			`spirit:version="bfm.design"/>`
102
103
104
105
106			`icarus`
107
108
109			`spirit:library="Testbench"`
110			`spirit:name="toolflow"`
111			`spirit:version="icarus"/>`
112
113
114
115
116
117
118
119			`commoncommon`
120			`Verilog`
121
122
123			`fs-common`
124
125
126
127
128			`sim:Simulation:`
129			`Verilog`
130
131
132			`fs-sim`
133
134
135
136
137
138			`lint:Lint:`
139			`Verilog`
140
141
142			`fs-sim`
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157			`fs-common`
158
159
160
161			`../verilog/tb.ext`
162			`verilogSourcefragment`
163
164
165
166
167
168
169
170
171			`fs-sim`
172
173
174
175			`../verilog/common/top.tb`
176			`verilogSourcemodule`
177
178
179
180
181
182
183
184
185			`fs-lint`
186
187
188
189			`../verilog/common/top.tb`
190			`verilogSourcemodule`
191
192
193
194
195
196
197
198
199
200
201
202
203
204
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [xml/] [disp_io_def_tb.xml] - Blame information for rev 131