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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [xml/] [disp_io_jtag_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
disp_io
jtag_tb
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      jtag.top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 
 
 

 
 
 
 
 

 
       
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="jtag_dut.params"/>
             
              
 
 
 
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="bfm.design"/>
              
 
 
              
              Jtag_Bfm
              
                                   spirit:library="logic"
                                   spirit:name="disp_io"
                                   spirit:version="jtag_bfm.design"/>
              
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
      
 
 

    JTAG_MODEL_SIZE4
    JTAG_MODEL_DIVCNT4'h4

 
 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/jtag.top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/jtag.top.tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 

 
 
 
 

Line No.	Rev	Author	Line
1	133	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`disp_io`
40			`jtag_tb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57			`jtag.top.tb`
58
59
60			`dest_dir`
61			`../verilog`
62
63
64			`top`
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84			`Params`
85
86
87			`spirit:library="logic"`
88			`spirit:name="disp_io"`
89			`spirit:version="jtag_dut.params"/>`
90
91
92
93
94
95
96
97			`Bfm`
98
99			`spirit:library="logic"`
100			`spirit:name="disp_io"`
101			`spirit:version="bfm.design"/>`
102
103
104
105
106			`Jtag_Bfm`
107
108			`spirit:library="logic"`
109			`spirit:name="disp_io"`
110			`spirit:version="jtag_bfm.design"/>`
111
112
113
114
115
116
117			`icarus`
118
119
120			`spirit:library="Testbench"`
121			`spirit:name="toolflow"`
122			`spirit:version="icarus"/>`
123
124
125
126
127
128
129
130			`commoncommon`
131			`Verilog`
132
133
134			`fs-common`
135
136
137
138
139			`sim:Simulation:`
140			`Verilog`
141
142
143			`fs-sim`
144
145
146
147
148
149			`lint:Lint:`
150			`Verilog`
151
152
153			`fs-sim`
154
155
156
157
158
159
160
161
162
163
164			`JTAG_MODEL_SIZE4`
165			`JTAG_MODEL_DIVCNT4'h4`
166
167
168
169
170
171
172
173
174
175
176
177			`fs-common`
178
179
180
181			`../verilog/tb.ext`
182			`verilogSourcefragment`
183
184
185
186
187
188
189
190
191			`fs-sim`
192
193
194
195			`../verilog/common/jtag.top.tb`
196			`verilogSourcemodule`
197
198
199
200
201
202
203
204
205			`fs-lint`
206
207
208
209			`../verilog/common/jtag.top.tb`
210			`verilogSourcemodule`
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
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227

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [xml/] [disp_io_jtag_tb.xml] - Blame information for rev 133