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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [rtl/] [xml/] [flash_memcontrl_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
flash_memcontrl
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="flash_memcontrl"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

ADDR_BITS24

 
 
 

 
 
addr
wire
in
ADDR_BITS-11

 
wdata
wire
in
150

 
cs
wire
in
10

 
rd
wire
in

 
wr
wire
in

 
stb
wire
in

 
ub
wire
in

 
lb
wire
in

 
wait_out
reg
out

 
rdata
wire
out
150

 
memadr_out
reg
out
ADDR_BITS-11

 
memdb_out
reg
out
150

 
memdb_oe
reg
out

 
memdb_in
wire
in
150

 
memoe_n_out
reg
out

 
memwr_n_out
reg
out

 
ramadv_n_out
reg
out

 
ramclk_out
reg
out

 
ramub_n_out
reg
out

 
ramlb_n_out
reg
out

 
ramcs_n_out
reg
out

 
ramcre_out
reg
out

 
ramwait_in
wire
in

 
flashcs_n_out
reg
out

 
flashrp_n_out
reg
out

 
flashststs_in
wire
in

 
 
 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [rtl/] [xml/] [flash_memcontrl_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`flash_memcontrl`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83			`gen_verilog`
84			`104.0`
85			`none`
86			`common`
87			`./tools/verilog/gen_verilog`
88
89
90			`destination`
91			`top`
92
93
94			`dest_dir`
95			`../verilog`
96
97
98
99
100
101
102
103
104
105
106
107
108
109			`fs-common`
110
111
112
113			`../verilog/top.body`
114			`verilogSourcefragment`
115
116
117
118
119
120
121
122
123
124			`fs-sim`
125
126
127
128			`../verilog/copyright.v`
129			`verilogSourceinclude`
130
131
132
133
134			`../verilog/common/top`
135			`verilogSourcemodule`
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154			`Hierarchical`
155
156
157			`spirit:library="logic"`
158			`spirit:name="flash_memcontrl"`
159			`spirit:version="def.design"/>`
160
161
162
163
164			`verilog`
165
166
167			`spirit:library="Testbench"`
168			`spirit:name="toolflow"`
169			`spirit:version="verilog"/>`
170
171
172
173
174
175
176
177
178			`commoncommon`
179
180			`Verilog`
181
182
183			`fs-common`
184
185
186
187
188
189			`sim:Simulation:`
190			`Verilog`
191
192
193			`fs-sim`
194
195
196
197
198			`syn:Synthesis:`
199			`Verilog`
200
201
202			`fs-sim`
203
204
205
206
207
208
209
210
211			`doc`
212
213
214			`spirit:library="Testbench"`
215			`spirit:name="toolflow"`
216			`spirit:version="documentation"/>`
217
218			`:Documentation:`
219			`Verilog`
220
221
222
223
224
225
226
227
228			`ADDR_BITS24`
229
230
231
232
233
234
235
236			`addr`
237			`wire`
238			`in`
239			`ADDR_BITS-11`
240
241
242			`wdata`
243			`wire`
244			`in`
245			`150`
246
247
248			`cs`
249			`wire`
250			`in`
251			`10`
252
253
254			`rd`
255			`wire`
256			`in`
257
258
259			`wr`
260			`wire`
261			`in`
262
263
264			`stb`
265			`wire`
266			`in`
267
268
269			`ub`
270			`wire`
271			`in`
272
273
274			`lb`
275			`wire`
276			`in`
277
278
279			`wait_out`
280			`reg`
281			`out`
282
283
284			`rdata`
285			`wire`
286			`out`
287			`150`
288
289
290			`memadr_out`
291			`reg`
292			`out`
293			`ADDR_BITS-11`
294
295
296			`memdb_out`
297			`reg`
298			`out`
299			`150`
300
301
302			`memdb_oe`
303			`reg`
304			`out`
305
306
307			`memdb_in`
308			`wire`
309			`in`
310			`150`
311
312
313			`memoe_n_out`
314			`reg`
315			`out`
316
317
318			`memwr_n_out`
319			`reg`
320			`out`
321
322
323			`ramadv_n_out`
324			`reg`
325			`out`
326
327
328			`ramclk_out`
329			`reg`
330			`out`
331
332
333			`ramub_n_out`
334			`reg`
335			`out`
336
337
338			`ramlb_n_out`
339			`reg`
340			`out`
341
342
343			`ramcs_n_out`
344			`reg`
345			`out`
346
347
348			`ramcre_out`
349			`reg`
350			`out`
351
352
353			`ramwait_in`
354			`wire`
355			`in`
356
357
358			`flashcs_n_out`
359			`reg`
360			`out`
361
362
363			`flashrp_n_out`
364			`reg`
365			`out`
366
367
368			`flashststs_in`
369			`wire`
370			`in`
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385