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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [rtl/] [xml/] [flash_memcontrl_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
flash_memcontrl
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="flash_memcontrl"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

ADDR_BITS24

 
 
 

 
 
addr
wire
in
ADDR_BITS-11

 
wdata
wire
in
150

 
cs
wire
in
10

 
rd
wire
in

 
wr
wire
in

 
stb
wire
in

 
ub
wire
in

 
lb
wire
in

 
wait_out
reg
out

 
rdata
wire
out
150

 
memadr_out
reg
out
ADDR_BITS-11

 
memdb_out
reg
out
150

 
memdb_oe
reg
out

 
memdb_in
wire
in
150

 
memoe_n_out
reg
out

 
memwr_n_out
reg
out

 
ramadv_n_out
reg
out

 
ramclk_out
reg
out

 
ramub_n_out
reg
out

 
ramlb_n_out
reg
out

 
ramcs_n_out
reg
out

 
ramcre_out
reg
out

 
ramwait_in
wire
in

 
flashcs_n_out
reg
out

 
flashrp_n_out
reg
out

 
flashststs_in
wire
in

 
 
 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [rtl/] [xml/] [flash_memcontrl_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`flash_memcontrl`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73
74
75
76
77	133	jt_eaton
78			`elab_verilog`
79			`102.1`
80			`none`
81			`:Simulation:`
82			`./tools/verilog/elab_verilog`
83
84
85			`dest_dir`
86			`io_ports`
87
88
89
90	131	jt_eaton
91
92
93
94
95
96			`gen_verilog`
97			`104.0`
98			`none`
99			`common`
100			`./tools/verilog/gen_verilog`
101
102
103			`destination`
104			`top`
105
106
107			`dest_dir`
108			`../verilog`
109
110
111
112
113
114
115
116
117
118
119
120
121
122			`fs-common`
123
124
125
126			`../verilog/top.body`
127			`verilogSourcefragment`
128
129
130
131
132
133
134
135
136
137			`fs-sim`
138
139
140
141			`../verilog/copyright.v`
142			`verilogSourceinclude`
143
144
145
146
147			`../verilog/common/top`
148			`verilogSourcemodule`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167			`Hierarchical`
168
169
170			`spirit:library="logic"`
171			`spirit:name="flash_memcontrl"`
172			`spirit:version="def.design"/>`
173
174
175
176
177			`verilog`
178
179
180			`spirit:library="Testbench"`
181			`spirit:name="toolflow"`
182			`spirit:version="verilog"/>`
183
184
185
186
187
188
189
190
191			`commoncommon`
192
193			`Verilog`
194
195
196			`fs-common`
197
198
199
200
201
202			`sim:Simulation:`
203			`Verilog`
204
205
206			`fs-sim`
207
208
209
210
211			`syn:Synthesis:`
212			`Verilog`
213
214
215			`fs-sim`
216
217
218
219
220
221
222
223
224			`doc`
225
226
227			`spirit:library="Testbench"`
228			`spirit:name="toolflow"`
229			`spirit:version="documentation"/>`
230
231			`:Documentation:`
232			`Verilog`
233
234
235
236
237
238
239
240
241			`ADDR_BITS24`
242
243
244
245
246
247
248
249			`addr`
250			`wire`
251			`in`
252			`ADDR_BITS-11`
253
254
255			`wdata`
256			`wire`
257			`in`
258			`150`
259
260
261			`cs`
262			`wire`
263			`in`
264			`10`
265
266
267			`rd`
268			`wire`
269			`in`
270
271
272			`wr`
273			`wire`
274			`in`
275
276
277			`stb`
278			`wire`
279			`in`
280
281
282			`ub`
283			`wire`
284			`in`
285
286
287			`lb`
288			`wire`
289			`in`
290
291
292			`wait_out`
293			`reg`
294			`out`
295
296
297			`rdata`
298			`wire`
299			`out`
300			`150`
301
302
303			`memadr_out`
304			`reg`
305			`out`
306			`ADDR_BITS-11`
307
308
309			`memdb_out`
310			`reg`
311			`out`
312			`150`
313
314
315			`memdb_oe`
316			`reg`
317			`out`
318
319
320			`memdb_in`
321			`wire`
322			`in`
323			`150`
324
325
326			`memoe_n_out`
327			`reg`
328			`out`
329
330
331			`memwr_n_out`
332			`reg`
333			`out`
334
335
336			`ramadv_n_out`
337			`reg`
338			`out`
339
340
341			`ramclk_out`
342			`reg`
343			`out`
344
345
346			`ramub_n_out`
347			`reg`
348			`out`
349
350
351			`ramlb_n_out`
352			`reg`
353			`out`
354
355
356			`ramcs_n_out`
357			`reg`
358			`out`
359
360
361			`ramcre_out`
362			`reg`
363			`out`
364
365
366			`ramwait_in`
367			`wire`
368			`in`
369
370
371			`flashcs_n_out`
372			`reg`
373			`out`
374
375
376			`flashrp_n_out`
377			`reg`
378			`out`
379
380
381			`flashststs_in`
382			`wire`
383			`in`
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398