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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [rtl/] [xml/] [flash_memcontrl_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
flash_memcontrl
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      flash_memcontrl_def
    
  

 
 
 

 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="flash_memcontrl"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

ADDR_BITS24

 
 
 

 
 
addr
wire
in
ADDR_BITS-11

 
wdata
wire
in
150

 
cs
wire
in
10

 
rd
wire
in

 
wr
wire
in

 
stb
wire
in

 
ub
wire
in

 
lb
wire
in

 
wait_out
reg
out

 
rdata
wire
out
150

 
memadr_out
reg
out
ADDR_BITS-11

 
memdb_out
reg
out
150

 
memdb_oe
reg
out

 
memdb_in
wire
in
150

 
memoe_n_out
reg
out

 
memwr_n_out
reg
out

 
ramadv_n_out
reg
out

 
ramclk_out
reg
out

 
ramub_n_out
reg
out

 
ramlb_n_out
reg
out

 
ramcs_n_out
reg
out

 
ramcre_out
reg
out

 
ramwait_in
wire
in

 
flashcs_n_out
reg
out

 
flashrp_n_out
reg
out

 
flashststs_in
wire
in

 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/flash_memcontrl_def
        verilogSourcemodule
      
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/flash_memcontrl_def
        verilogSourcemodule
      
 
    
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [rtl/] [xml/] [flash_memcontrl_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`flash_memcontrl`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73
74
75
76	133	jt_eaton
77	131	jt_eaton	`gen_verilog`
78			`104.0`
79			`none`
80			`common`
81			`./tools/verilog/gen_verilog`
82
83
84			`destination`
85	134	jt_eaton	`flash_memcontrl_def`
86	131	jt_eaton
87
88
89
90
91
92
93
94
95
96
97
98
99
100			`Hierarchical`
101
102
103			`spirit:library="logic"`
104			`spirit:name="flash_memcontrl"`
105			`spirit:version="def.design"/>`
106
107
108
109
110			`verilog`
111
112
113			`spirit:library="Testbench"`
114			`spirit:name="toolflow"`
115			`spirit:version="verilog"/>`
116
117
118
119
120
121
122
123
124			`commoncommon`
125
126			`Verilog`
127
128
129			`fs-common`
130
131
132
133
134
135			`sim:Simulation:`
136			`Verilog`
137
138
139			`fs-sim`
140
141
142
143
144			`syn:Synthesis:`
145			`Verilog`
146
147
148			`fs-sim`
149
150
151
152
153
154
155
156
157			`doc`
158
159
160			`spirit:library="Testbench"`
161			`spirit:name="toolflow"`
162			`spirit:version="documentation"/>`
163
164			`:Documentation:`
165			`Verilog`
166
167
168
169
170
171
172
173
174			`ADDR_BITS24`
175
176
177
178
179
180
181
182			`addr`
183			`wire`
184			`in`
185			`ADDR_BITS-11`
186
187
188			`wdata`
189			`wire`
190			`in`
191			`150`
192
193
194			`cs`
195			`wire`
196			`in`
197			`10`
198
199
200			`rd`
201			`wire`
202			`in`
203
204
205			`wr`
206			`wire`
207			`in`
208
209
210			`stb`
211			`wire`
212			`in`
213
214
215			`ub`
216			`wire`
217			`in`
218
219
220			`lb`
221			`wire`
222			`in`
223
224
225			`wait_out`
226			`reg`
227			`out`
228
229
230			`rdata`
231			`wire`
232			`out`
233			`150`
234
235
236			`memadr_out`
237			`reg`
238			`out`
239			`ADDR_BITS-11`
240
241
242			`memdb_out`
243			`reg`
244			`out`
245			`150`
246
247
248			`memdb_oe`
249			`reg`
250			`out`
251
252
253			`memdb_in`
254			`wire`
255			`in`
256			`150`
257
258
259			`memoe_n_out`
260			`reg`
261			`out`
262
263
264			`memwr_n_out`
265			`reg`
266			`out`
267
268
269			`ramadv_n_out`
270			`reg`
271			`out`
272
273
274			`ramclk_out`
275			`reg`
276			`out`
277
278
279			`ramub_n_out`
280			`reg`
281			`out`
282
283
284			`ramlb_n_out`
285			`reg`
286			`out`
287
288
289			`ramcs_n_out`
290			`reg`
291			`out`
292
293
294			`ramcre_out`
295			`reg`
296			`out`
297
298
299			`ramwait_in`
300			`wire`
301			`in`
302
303
304			`flashcs_n_out`
305			`reg`
306			`out`
307
308
309			`flashrp_n_out`
310			`reg`
311			`out`
312
313
314			`flashststs_in`
315			`wire`
316			`in`
317
318
319
320
321
322
323
324
325
326	134	jt_eaton
327	131	jt_eaton
328	134	jt_eaton
329			`fs-common`
330	131	jt_eaton
331	134	jt_eaton
332
333			`../verilog/top.body`
334			`verilogSourcefragment`
335
336	131	jt_eaton
337	134	jt_eaton
338	131	jt_eaton
339
340	134	jt_eaton
341			`fs-sim`
342
343
344
345			`../verilog/copyright`
346			`verilogSourceinclude`
347
348
349
350
351			`../verilog/common/flash_memcontrl_def`
352			`verilogSourcemodule`
353
354
355
356
357
358
359
360			`fs-syn`
361
362
363
364			`../verilog/copyright`
365			`verilogSourceinclude`
366
367
368
369
370			`../verilog/common/flash_memcontrl_def`
371			`verilogSourcemodule`
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390	131	jt_eaton