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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [sim/] [icarus/] [default/] [wave.sav] - Blame information for rev 133

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Line No. Rev Author Line
1 133 jt_eaton
[*]
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[*] GTKWave Analyzer v3.3.62 (w)1999-2014 BSI
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[*] Wed Apr 22 16:46:48 2015
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[*]
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[dumpfile] "/home/johne/Desktop/socgen/work/opencores.org__logic/ip/flash_memcontrl/sim/icarus/default/TestBench.vcd"
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[dumpfile_mtime] "Wed Apr 22 16:21:05 2015"
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[dumpfile_size] 31324
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[savefile] "/home/johne/Desktop/socgen/Projects/opencores.org/logic/ip/flash_memcontrl/sim/icarus/default/wave.sav"
9 131 jt_eaton
[timestart] 0
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[size] 1613 999
11 133 jt_eaton
[pos] 75 339
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*-13.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
13 131 jt_eaton
[treeopen] TB.
14 133 jt_eaton
[treeopen] TB.test.
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[treeopen] TB.test.BUS16.
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[sst_width] 223
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[signals_width] 158
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[sst_expanded] 1
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[sst_vpaned_height] 300
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@22
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TB.test.memadr_out[23:1]
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TB.test.memdb_in[15:0]
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TB.test.memdb_io[15:0]
24 131 jt_eaton
@28
25 133 jt_eaton
TB.test.memdb_oe
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@22
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TB.test.memdb_out[15:0]
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@28
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TB.test.memoe_n_out
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TB.test.memwr_n_out
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TB.test.ramadv_n_out
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TB.test.ramclk_out
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TB.test.ramcre_out
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TB.test.ramcs_n_out
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TB.test.ramlb_n_out
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TB.test.ramub_n_out
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TB.test.ramwait_in
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TB.test.ramwait_n
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TB.test.rd
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@22
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TB.test.rdata[15:0]
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@28
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TB.test.reset
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TB.test.stb
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TB.test.ub
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TB.test.wait_out
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@22
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TB.test.wdata[15:0]
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@28
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TB.test.wr
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@22
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TB.test.psram.addr[22:0]
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@28
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TB.test.psram.o_wait
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TB.test.psram.adv_n
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TB.test.psram.ce_n
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TB.test.psram.clk
58 131 jt_eaton
@29
59 133 jt_eaton
TB.test.psram.cre
60 131 jt_eaton
[pattern_trace] 1
61
[pattern_trace] 0

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