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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
 
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assign    stb         =|cs;
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wire [15:0]        memdb_io;
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wire               addr_0;
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micro_bus16_model_def
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bus16
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 (
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    .clk           ( clk    ),
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    .reset         ( reset  ),
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    .addr          ( {addr,addr_0}   ),
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    .wdata         ( wdata  ),
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    .cs            ( cs     ),
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    .rd            ( rd     ),
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    .wr            ( wr     ),
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    .ub            ( ub     ),
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    .lb            ( lb     ),
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    .rdata         ( rdata  )
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);
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cde_pad_se_dig #(.WIDTH(16))
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 memdb_buff
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  (
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   .pad_out     ( memdb_out ),
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   .pad_oe      ( memdb_oe  ),
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   .pad_in      ( memdb_in  ),
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   .PAD         ( memdb_io  )
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   );
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pullup pu_ramwait ( ramwait_n );
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mt45w8mw12_def
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psram (
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    .clk    ( ramclk_out    ),
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    .adv_n  ( ramadv_n_out  ),
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    .cre    ( ramcre_out    ),
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    .o_wait ( ramwait_n     ),
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    .ce_n   ( ramcs_n_out   ),
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    .oe_n   ( memoe_n_out   ),
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    .we_n   ( memwr_n_out   ),
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    .lb_n   ( ramlb_n_out   ),
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    .ub_n   ( ramub_n_out   ),
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    .addr   ( memadr_out    ),
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    .dq     ( memdb_io      )
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);
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assign STOP = 1'b0;
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assign BAD = 1'b0;
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