URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [componentCfg.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
logic
micro_bus
 
 
2
_
_
_
VARIANT
 

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 

 
/doc
 

 
    
 
         
            default
            def
            
            ADD16
            CH0_BITS4
            CH0_MATCH4'h0
            CH1_BITS4
            CH1_MATCH4'h0
            CH2_BITS4
            CH2_MATCH4'h0
            CH3_BITS4
            CH3_MATCH4'h0
            CH4_BITS4
            CH4_MATCH4'h0
            CH5_BITS4
            CH5_MATCH4'h0
           
          
 
 
 
 
         
            exp_default
            exp5
            exp6
            exp9
            
            SLA_ADD_WIDTH8
            SLA_DATA_WIDTH16
            MAS_ADD_WIDTH4
            MAS_DATA_WIDTH8
 
           
          
 
      
 

 
 
micro_bus/sim
 
 
 
 
 

 
 
 

micro_bus_def_tb
def_tb
default

    PERIOD40
    TIMEOUT100000


  
  micro_bus_defTB.test.dut
  


  icaruscoverage


 
 

micro_bus
micro_bus_def_lint
def_lint
default

  rtl_check


 
 
 

 
 
 
 
 
 

 

default
micro_bus_def_lint

            ADD16
            CH0_BITS4
            CH0_MATCH4'h0
            CH1_BITS4
            CH1_MATCH4'h2
            CH2_BITS8
            CH2_MATCH8'h03
            CH3_BITS2
            CH3_MATCH2'b10
            CH4_BITS4
            CH4_MATCH4'h9
            CH5_BITS4
            CH5_MATCH4'hf


 

 
 
 
 


default
micro_bus_def_tb

            ADD16
            CH0_BITS4
            CH0_MATCH4'h0
            CH1_BITS4
            CH1_MATCH4'h2
            CH2_BITS4
            CH2_MATCH4'h3
            CH3_BITS4
            CH3_MATCH4'h8
            CH4_BITS4
            CH4_MATCH4'h9
            CH5_BITS4
            CH5_MATCH4'hf


 
 
 

 

 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`logic`
12			`micro_bus`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20
21	135	jt_eaton
22
23			`TestBenches`
24			`sim`
25			`testbenches`
26			`testbench`
27			`version`
28
29
30			`Fpgas`
31			`syn`
32			`ise`
33			`chip`
34			`variant`
35
36
37	131	jt_eaton
38	135	jt_eaton
39
40	131	jt_eaton
41
42			`/doc`
43
44
45
46	133	jt_eaton
47	131	jt_eaton
48	133	jt_eaton
49			`default`
50	134	jt_eaton	`def`
51	133	jt_eaton
52	134	jt_eaton	`ADD16`
53	133	jt_eaton	`CH0_BITS4`
54			`CH0_MATCH4'h0`
55			`CH1_BITS4`
56			`CH1_MATCH4'h0`
57			`CH2_BITS4`
58			`CH2_MATCH4'h0`
59			`CH3_BITS4`
60			`CH3_MATCH4'h0`
61			`CH4_BITS4`
62			`CH4_MATCH4'h0`
63			`CH5_BITS4`
64			`CH5_MATCH4'h0`
65
66
67	131	jt_eaton
68
69
70	133	jt_eaton
71
72			`exp_default`
73	134	jt_eaton	`exp5`
74			`exp6`
75			`exp9`
76	133	jt_eaton
77			`SLA_ADD_WIDTH8`
78			`SLA_DATA_WIDTH16`
79			`MAS_ADD_WIDTH4`
80			`MAS_DATA_WIDTH8`
81
82
83
84
85
86
87	131	jt_eaton
88
89
90			`micro_bus/sim`
91
92
93
94
95
96
97
98
99
100
101			`micro_bus_def_tb`
102			`def_tb`
103	133	jt_eaton	`default`
104	131	jt_eaton
105			`PERIOD40`
106			`TIMEOUT100000`
107
108
109
110			`micro_bus_defTB.test.dut`
111
112
113
114			`icaruscoverage`
115
116
117
118
119
120			`micro_bus`
121			`micro_bus_def_lint`
122			`def_lint`
123	133	jt_eaton	`default`
124	131	jt_eaton
125			`rtl_check`
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141			`default`
142			`micro_bus_def_lint`
143	134	jt_eaton
144			`ADD16`
145			`CH0_BITS4`
146			`CH0_MATCH4'h0`
147			`CH1_BITS4`
148			`CH1_MATCH4'h2`
149			`CH2_BITS8`
150			`CH2_MATCH8'h03`
151			`CH3_BITS2`
152			`CH3_MATCH2'b10`
153			`CH4_BITS4`
154			`CH4_MATCH4'h9`
155			`CH5_BITS4`
156			`CH5_MATCH4'hf`
157
158	131	jt_eaton
159
160
161
162
163
164
165
166
167			`default`
168			`micro_bus_def_tb`
169
170	134	jt_eaton	`ADD16`
171			`CH0_BITS4`
172			`CH0_MATCH4'h0`
173			`CH1_BITS4`
174			`CH1_MATCH4'h2`
175			`CH2_BITS4`
176			`CH2_MATCH4'h3`
177			`CH3_BITS4`
178			`CH3_MATCH4'h8`
179			`CH4_BITS4`
180			`CH4_MATCH4'h9`
181			`CH5_BITS4`
182			`CH5_MATCH4'hf`
183	131	jt_eaton
184
185
186
187
188
189
190
191
192
193
194

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [componentCfg.xml] - Blame information for rev 135