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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [componentCfg.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
logic
micro_bus
 
 
2
_
_
_
VARIANT
 
 

 
/doc
 

 
    
 
         
            default
            
            ADD0
            CH0_BITS4
            CH0_MATCH4'h0
            CH1_BITS4
            CH1_MATCH4'h0
            CH2_BITS4
            CH2_MATCH4'h0
            CH3_BITS4
            CH3_MATCH4'h0
            CH4_BITS4
            CH4_MATCH4'h0
            CH5_BITS4
            CH5_MATCH4'h0
           
          
 
 
 
 
         
            exp_default
            
            SLA_ADD_WIDTH8
            SLA_DATA_WIDTH16
            MAS_ADD_WIDTH4
            MAS_DATA_WIDTH8
 
           
          
 
      
 

 
 
micro_bus/sim
 
 
 
 
 

 
 
 

micro_bus_def_tb
def_tb
default

    PERIOD40
    TIMEOUT100000


  
  micro_bus_defTB.test.dut
  


  icaruscoverage


 
 

micro_bus
micro_bus_def_lint
def_lint
default

  rtl_check


 
 
 

 
 
 
 
 
 

 

default
micro_bus_def_lint

 

 
 
 
 


default
micro_bus_def_tb

PERIOD20


 
 
 

 

 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`logic`
12			`micro_bus`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20
21
22
23
24			`/doc`
25
26
27
28	133	jt_eaton
29	131	jt_eaton
30	133	jt_eaton
31			`default`
32
33			`ADD0`
34			`CH0_BITS4`
35			`CH0_MATCH4'h0`
36			`CH1_BITS4`
37			`CH1_MATCH4'h0`
38			`CH2_BITS4`
39			`CH2_MATCH4'h0`
40			`CH3_BITS4`
41			`CH3_MATCH4'h0`
42			`CH4_BITS4`
43			`CH4_MATCH4'h0`
44			`CH5_BITS4`
45			`CH5_MATCH4'h0`
46
47
48	131	jt_eaton
49
50
51	133	jt_eaton
52
53			`exp_default`
54
55			`SLA_ADD_WIDTH8`
56			`SLA_DATA_WIDTH16`
57			`MAS_ADD_WIDTH4`
58			`MAS_DATA_WIDTH8`
59
60
61
62
63
64
65	131	jt_eaton
66
67
68			`micro_bus/sim`
69
70
71
72
73
74
75
76
77
78
79			`micro_bus_def_tb`
80			`def_tb`
81	133	jt_eaton	`default`
82	131	jt_eaton
83			`PERIOD40`
84			`TIMEOUT100000`
85
86
87
88			`micro_bus_defTB.test.dut`
89
90
91
92			`icaruscoverage`
93
94
95
96
97
98			`micro_bus`
99			`micro_bus_def_lint`
100			`def_lint`
101	133	jt_eaton	`default`
102	131	jt_eaton
103			`rtl_check`
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119			`default`
120			`micro_bus_def_lint`
121
122
123
124
125
126
127
128
129
130			`default`
131			`micro_bus_def_tb`
132
133			`PERIOD20`
134
135
136
137
138
139
140
141
142
143
144
145

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [componentCfg.xml] - Blame information for rev 133