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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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always@(*)
 begin
 if(addr_in[15:8] == 8'h00)     mem_cs         = 1'b1;
 else                            mem_cs         = 1'b0;
 end
 
 reg CS0_r;
 
 
 
always@(posedge clk)
 
begin
     CS0_r  <=     mem_cs;
end
 
 
 
 
 
 
 reg mem_cs2;
 reg CSP_r;
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b1111)  mem_cs2         = 1'b1;
 else                            mem_cs2         = 1'b0;
 end
 
always@(posedge clk)
     begin
     CSP_r  <=     mem_cs2;
     end
 
 
 
 
 
 reg mem_cs3;
 reg CSI_r;
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b1000)  mem_cs3         = 1'b1;
 else                            mem_cs3         = 1'b0;
 end
 
always@(posedge clk)
 
begin
     CSI_r  <=    mem_cs3 ;
end
 
 
 
 
 reg mem_cs4;
 reg CSB_r;
 
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b1100)  mem_cs4          = 1'b1;
 else                            mem_cs4          = 1'b0;
 end
 
always@(posedge clk)
 
begin
     CSB_r  <=     mem_cs4;
end
 
 
 
 
 
 
 
 reg mem_cs5;
 reg CSE_r;
 
always@(*)
 begin
 if(addr_in[15:14] == 2'b01)    mem_cs5         = 1'b1;
 else                            mem_cs5         = 1'b0;
 end
 
 
 
 
always@(posedge clk)
 
begin
     CSE_r  <=     mem_cs5;
end
 
 
 
 
 
 
 
 
 
 
 
 
 
assign mem_addr   = addr_in;
assign mem_rd     = rd_in;
assign mem_wr     = wr_in;
assign mem_wdata  = {wdata_in,wdata_in};
assign enable     = ~( ext_mem_wait || io_reg_wait  );
 
 
 
reg data_cs_r;
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b0000)   data_cs           = 1'b1;
 else                            data_cs           = 1'b0;
 end
 
always@(posedge clk)
 
begin
     data_cs_r  <=     data_cs;
end
 
assign data_addr            = addr_in[11:1];
assign data_rd              = rd_in;
assign data_wr              = wr_in;
assign data_wdata           = {wdata_in,wdata_in};
assign data_be[0]           = !addr_in[0];
assign data_be[1]           =  addr_in[0];
 
 
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b1000)   io_reg_cs           = 1'b1;
 else                            io_reg_cs           = 1'b0;
 end
assign io_reg_addr            = addr_in[11:0];
assign io_reg_rd              = rd_in;
assign io_reg_wr              = wr_in;
assign io_reg_wdata           = wdata_in;
 
 
always@(*)
 begin
 if(addr_in[15:14] == 2'b01)     ext_mem_cs            = 1'b1;
 else                            ext_mem_cs            = 1'b0;
 end
 
assign ext_mem_addr            = addr_in[13:0];
assign ext_mem_rd              = rd_in;
assign ext_mem_wr              = wr_in;
assign ext_mem_wdata           = {wdata_in,wdata_in};
 
 
 
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b1100)   prog_rom_mem_cs          = 1'b1;
 else                            prog_rom_mem_cs          = 1'b0;
 end
 
 
assign prog_rom_mem_addr            = addr_in[11:0];
assign prog_rom_mem_rd              = rd_in;
assign prog_rom_mem_wr              = wr_in;
assign prog_rom_mem_wdata           = {wdata_in,wdata_in};
 
 
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b1111)  sh_prog_rom_mem_cs         = 1'b1;
 else                           sh_prog_rom_mem_cs         = 1'b0;
 end
 
 
assign sh_prog_rom_mem_addr            = addr_in[11:0];
assign sh_prog_rom_mem_rd              = rd_in;
assign sh_prog_rom_mem_wr              = wr_in;
assign sh_prog_rom_mem_wdata           = {wdata_in,wdata_in};
 
 
 
 
always@(*)
if ( CS0_r )       rdata_out = mem_rdata;
else
if ( data_cs_r )   rdata_out = data_rdata;
else
if ( CSB_r )       rdata_out = prog_rom_mem_rdata;
else
if ( CSI_r )       rdata_out = io_reg_rdata;
else
if ( CSP_r )       rdata_out = sh_prog_rom_mem_rdata;
else               rdata_out = ext_mem_rdata;

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3			`always@(*)`
4			`begin`
5			`if(addr_in[15:8] == 8'h00) mem_cs = 1'b1;`
6			`else mem_cs = 1'b0;`
7			`end`
8
9			`reg CS0_r;`
10
11
12
13			`always@(posedge clk)`
14
15			`begin`
16			`CS0_r <= mem_cs;`
17			`end`
18
19
20
21
22
23
24			`reg mem_cs2;`
25			`reg CSP_r;`
26
27			`always@(*)`
28			`begin`
29			`if(addr_in[15:12] == 4'b1111) mem_cs2 = 1'b1;`
30			`else mem_cs2 = 1'b0;`
31			`end`
32
33			`always@(posedge clk)`
34			`begin`
35			`CSP_r <= mem_cs2;`
36			`end`
37
38
39
40
41
42			`reg mem_cs3;`
43			`reg CSI_r;`
44
45			`always@(*)`
46			`begin`
47			`if(addr_in[15:12] == 4'b1000) mem_cs3 = 1'b1;`
48			`else mem_cs3 = 1'b0;`
49			`end`
50
51			`always@(posedge clk)`
52
53			`begin`
54			`CSI_r <= mem_cs3 ;`
55			`end`
56
57
58
59
60			`reg mem_cs4;`
61			`reg CSB_r;`
62
63
64			`always@(*)`
65			`begin`
66			`if(addr_in[15:12] == 4'b1100) mem_cs4 = 1'b1;`
67			`else mem_cs4 = 1'b0;`
68			`end`
69
70			`always@(posedge clk)`
71
72			`begin`
73			`CSB_r <= mem_cs4;`
74			`end`
75
76
77
78
79
80
81
82			`reg mem_cs5;`
83			`reg CSE_r;`
84
85			`always@(*)`
86			`begin`
87			`if(addr_in[15:14] == 2'b01) mem_cs5 = 1'b1;`
88			`else mem_cs5 = 1'b0;`
89			`end`
90
91
92
93
94			`always@(posedge clk)`
95
96			`begin`
97			`CSE_r <= mem_cs5;`
98			`end`
99
100
101
102
103
104
105
106
107
108
109
110
111
112			`assign mem_addr = addr_in;`
113			`assign mem_rd = rd_in;`
114			`assign mem_wr = wr_in;`
115			`assign mem_wdata = {wdata_in,wdata_in};`
116			`assign enable = ~( ext_mem_wait \|\| io_reg_wait );`
117
118
119
120			`reg data_cs_r;`
121
122			`always@(*)`
123			`begin`
124			`if(addr_in[15:12] == 4'b0000) data_cs = 1'b1;`
125			`else data_cs = 1'b0;`
126			`end`
127
128			`always@(posedge clk)`
129
130			`begin`
131			`data_cs_r <= data_cs;`
132			`end`
133
134			`assign data_addr = addr_in[11:1];`
135			`assign data_rd = rd_in;`
136			`assign data_wr = wr_in;`
137			`assign data_wdata = {wdata_in,wdata_in};`
138			`assign data_be[0] = !addr_in[0];`
139			`assign data_be[1] = addr_in[0];`
140
141
142
143			`always@(*)`
144			`begin`
145			`if(addr_in[15:12] == 4'b1000) io_reg_cs = 1'b1;`
146			`else io_reg_cs = 1'b0;`
147			`end`
148			`assign io_reg_addr = addr_in[11:0];`
149			`assign io_reg_rd = rd_in;`
150			`assign io_reg_wr = wr_in;`
151			`assign io_reg_wdata = wdata_in;`
152
153
154			`always@(*)`
155			`begin`
156			`if(addr_in[15:14] == 2'b01) ext_mem_cs = 1'b1;`
157			`else ext_mem_cs = 1'b0;`
158			`end`
159
160			`assign ext_mem_addr = addr_in[13:0];`
161			`assign ext_mem_rd = rd_in;`
162			`assign ext_mem_wr = wr_in;`
163			`assign ext_mem_wdata = {wdata_in,wdata_in};`
164
165
166
167
168			`always@(*)`
169			`begin`
170			`if(addr_in[15:12] == 4'b1100) prog_rom_mem_cs = 1'b1;`
171			`else prog_rom_mem_cs = 1'b0;`
172			`end`
173
174
175			`assign prog_rom_mem_addr = addr_in[11:0];`
176			`assign prog_rom_mem_rd = rd_in;`
177			`assign prog_rom_mem_wr = wr_in;`
178			`assign prog_rom_mem_wdata = {wdata_in,wdata_in};`
179
180
181
182			`always@(*)`
183			`begin`
184			`if(addr_in[15:12] == 4'b1111) sh_prog_rom_mem_cs = 1'b1;`
185			`else sh_prog_rom_mem_cs = 1'b0;`
186			`end`
187
188
189			`assign sh_prog_rom_mem_addr = addr_in[11:0];`
190			`assign sh_prog_rom_mem_rd = rd_in;`
191			`assign sh_prog_rom_mem_wr = wr_in;`
192			`assign sh_prog_rom_mem_wdata = {wdata_in,wdata_in};`
193
194
195
196
197			`always@(*)`
198			`if ( CS0_r ) rdata_out = mem_rdata;`
199			`else`
200			`if ( data_cs_r ) rdata_out = data_rdata;`
201			`else`
202			`if ( CSB_r ) rdata_out = prog_rom_mem_rdata;`
203			`else`
204			`if ( CSI_r ) rdata_out = io_reg_rdata;`
205			`else`
206			`if ( CSP_r ) rdata_out = sh_prog_rom_mem_rdata;`
207			`else rdata_out = ext_mem_rdata;`