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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [verilog/] [top.body] - Blame information for rev 134

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Line No. Rev Author Line
1 134 jt_eaton 
 
2 
 
3 
assign enable     = ~( ext_mem_wait || io_reg_wait  );
4 
 
5 
 
6 
 
7 
/*   CH0   */
8 
 
9 
reg mem_cs_r;
10 131 jt_eaton 
 
11 
 
12 134 jt_eaton 
always@(addr_in)
13 131 jt_eaton 
 begin
14 134 jt_eaton 
 if(addr_in[ADD-1:ADD-CH0_BITS] == CH0_MATCH)      mem_cs         = 1'b1;
15 
 else                                              mem_cs         = 1'b0;
16 131 jt_eaton 
 end
17 
 
18 
 
19 
always@(posedge clk)
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21 
begin
22 133 jt_eaton 
     mem_cs_r  <=     mem_cs;
23 131 jt_eaton 
end
24 
 
25 133 jt_eaton 
 
26 
assign mem_addr   = addr_in;
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assign mem_rd     = rd_in;
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assign mem_wr     = wr_in;
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assign mem_wdata  = {wdata_in,wdata_in};
30 131 jt_eaton 
 
31 
 
32 
 
33 
 
34 
 
35 
 
36 134 jt_eaton 
/*   CH1   */
37 
 
38 133 jt_eaton 
reg data_cs_r;
39 
 
40 134 jt_eaton 
always@(addr_in)
41 131 jt_eaton 
 begin
42 134 jt_eaton 
 if(addr_in[ADD-1:ADD-CH1_BITS] == CH1_MATCH)   data_cs           = 1'b1;
43 
 else                                           data_cs           = 1'b0;
44 131 jt_eaton 
 end
45 
 
46 
always@(posedge clk)
47 133 jt_eaton 
begin
48 
     data_cs_r  <=     data_cs;
49 
end
50 131 jt_eaton 
 
51 134 jt_eaton 
assign data_addr            = addr_in[ADD-CH1_BITS-1:1];
52 133 jt_eaton 
assign data_rd              = rd_in;
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assign data_wr              = wr_in;
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assign data_wdata           = {wdata_in,wdata_in};
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assign data_be[0]           = !addr_in[0];
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assign data_be[1]           =  addr_in[0];
57 131 jt_eaton 
 
58 
 
59 134 jt_eaton 
/*   CH2   */
60 133 jt_eaton 
reg io_reg_cs_r;
61 131 jt_eaton 
 
62 134 jt_eaton 
always@(addr_in)
63 131 jt_eaton 
 begin
64 134 jt_eaton 
 if(addr_in[ADD-1:ADD-CH2_BITS] == CH2_MATCH)   io_reg_cs           = 1'b1;
65 133 jt_eaton 
 else                               io_reg_cs           = 1'b0;
66 
 end
67 131 jt_eaton 
 
68 
always@(posedge clk)
69 
 
70 
begin
71 133 jt_eaton 
     io_reg_cs_r  <=     io_reg_cs;
72 131 jt_eaton 
end
73 
 
74 
 
75 134 jt_eaton 
assign io_reg_addr            = addr_in[ADD-CH2_BITS-1:0];
76 133 jt_eaton 
assign io_reg_rd              = rd_in;
77 
assign io_reg_wr              = wr_in;
78 
assign io_reg_wdata           = wdata_in;
79 131 jt_eaton 
 
80 134 jt_eaton 
/*   CH3   */
81 131 jt_eaton 
 
82 133 jt_eaton 
reg ext_mem_cs_r;
83 
 
84 134 jt_eaton 
always@(addr_in)
85 131 jt_eaton 
 begin
86 134 jt_eaton 
 if(addr_in[ADD-1:ADD-CH3_BITS] == CH3_MATCH)     ext_mem_cs            = 1'b1;
87 
 else                                             ext_mem_cs            = 1'b0;
88 131 jt_eaton 
 end
89 
 
90 
 
91 
always@(posedge clk)
92 
 
93 
begin
94 133 jt_eaton 
     ext_mem_cs_r  <=     ext_mem_cs;
95 131 jt_eaton 
end
96 
 
97 134 jt_eaton 
assign ext_mem_addr            = addr_in[ADD-CH3_BITS-1:0];
98 133 jt_eaton 
assign ext_mem_rd              = rd_in;
99 
assign ext_mem_wr              = wr_in;
100 
assign ext_mem_wdata           = {wdata_in,wdata_in};
101 131 jt_eaton 
 
102 
 
103 134 jt_eaton 
/*   CH4   */
104 131 jt_eaton 
 
105 133 jt_eaton 
reg prog_rom_mem_cs_r;
106 131 jt_eaton 
 
107 
 
108 134 jt_eaton 
always@(addr_in)
109 131 jt_eaton 
 begin
110 134 jt_eaton 
 if(addr_in[ADD-1:ADD-CH4_BITS] == CH4_MATCH)   prog_rom_mem_cs          = 1'b1;
111 
 else                                           prog_rom_mem_cs          = 1'b0;
112 133 jt_eaton 
 end
113 131 jt_eaton 
 
114 
always@(posedge clk)
115 
 
116 
begin
117 133 jt_eaton 
     prog_rom_mem_cs_r  <=     prog_rom_mem_cs;
118 131 jt_eaton 
end
119 134 jt_eaton 
assign prog_rom_mem_addr            = addr_in[ADD-CH4_BITS-1:0];
120 133 jt_eaton 
assign prog_rom_mem_rd              = rd_in;
121 
assign prog_rom_mem_wr              = wr_in;
122 
assign prog_rom_mem_wdata           = {wdata_in,wdata_in};
123 131 jt_eaton 
 
124 134 jt_eaton 
/*   CH5   */
125 131 jt_eaton 
 
126 
 
127 133 jt_eaton 
reg sh_prog_rom_mem_cs_r;
128 131 jt_eaton 
 
129 134 jt_eaton 
always@(addr_in)
130 131 jt_eaton 
 begin
131 134 jt_eaton 
 if(addr_in[ADD-1:ADD-CH5_BITS] == CH5_MATCH)  sh_prog_rom_mem_cs         = 1'b1;
132 
 else                                          sh_prog_rom_mem_cs         = 1'b0;
133 131 jt_eaton 
 end
134 
 
135 
 
136 133 jt_eaton 
always@(posedge clk)
137 
 
138 
begin
139 
     sh_prog_rom_mem_cs_r  <=     sh_prog_rom_mem_cs;
140 
end
141 
 
142 134 jt_eaton 
assign sh_prog_rom_mem_addr            = addr_in[ADD-CH5_BITS-1:0];
143 131 jt_eaton 
assign sh_prog_rom_mem_rd              = rd_in;
144 
assign sh_prog_rom_mem_wr              = wr_in;
145 
assign sh_prog_rom_mem_wdata           = {wdata_in,wdata_in};
146 
 
147 
 
148 
 
149 
 
150 133 jt_eaton 
 
151 
 
152 
 
153 
 
154 131 jt_eaton 
always@(*)
155 133 jt_eaton 
if ( mem_cs_r )                   rdata_out = mem_rdata;
156 131 jt_eaton 
else
157 133 jt_eaton 
if ( data_cs_r )                  rdata_out = data_rdata;
158 131 jt_eaton 
else
159 133 jt_eaton 
if ( prog_rom_mem_cs_r )          rdata_out = prog_rom_mem_rdata;
160 131 jt_eaton 
else
161 133 jt_eaton 
if ( io_reg_cs_r )                rdata_out = io_reg_rdata;
162 131 jt_eaton 
else
163 133 jt_eaton 
if ( sh_prog_rom_mem_cs_r )       rdata_out = sh_prog_rom_mem_rdata;
164 
else                              rdata_out = ext_mem_rdata;

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