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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [verilog/] [top.body.byte] - Blame information for rev 131

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reg [4:0] mem_cs_r;
 
 
 always@(posedge clk)     mem_cs_r  <=     mem_cs;
 
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b0000)     mem_cs[0]         = 1'b1;
 else                             mem_cs[0]         = 1'b0;
 end
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b1111)   mem_cs[1]         = 1'b1;
 else                             mem_cs[1]         = 1'b0;
 end
 
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b1100)   mem_cs[2]         = 1'b1;
 else                            mem_cs[2]         = 1'b0;
 end
 
 
always@(*)
 begin
 if(addr_in[15:12] == 4'b1000)  mem_cs[3]         = 1'b1;
 else                            mem_cs[3]         = 1'b0;
 end
 
 
 
 
always@(*)
 begin
 if(addr_in[15:14] == 2'b01)  mem_cs[4]          = 1'b1;
 else                            mem_cs[4]          = 1'b0;
 end
 
 
 
 
 
 
 
 
 
 
always@(*)
if ( mem_cs_r[0] ) rdata_out = mem_rdata[7:0];
else
if ( mem_cs_r[1] ) rdata_out = mem_rdata[15:8];
else
if ( mem_cs_r[2] ) rdata_out = mem_rdata[23:16];
else
if ( mem_cs_r[3] ) rdata_out = mem_rdata[31:24];
else               rdata_out = addr_in[0]?mem_rdata[47:40]:mem_rdata[39:32];
 
 
 
 
 
assign mem_addr   =  addr_in;
assign mem_rd     =  rd_in;
assign mem_wr     =  wr_in;
assign mem_wdata  = {wdata_in,wdata_in};
assign enable     = ~(|mem_wait);
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`reg [4:0] mem_cs_r;`
2
3
4			`always@(posedge clk) mem_cs_r <= mem_cs;`
5
6
7			`always@(*)`
8			`begin`
9			`if(addr_in[15:12] == 4'b0000) mem_cs[0] = 1'b1;`
10			`else mem_cs[0] = 1'b0;`
11			`end`
12
13			`always@(*)`
14			`begin`
15			`if(addr_in[15:12] == 4'b1111) mem_cs[1] = 1'b1;`
16			`else mem_cs[1] = 1'b0;`
17			`end`
18
19
20			`always@(*)`
21			`begin`
22			`if(addr_in[15:12] == 4'b1100) mem_cs[2] = 1'b1;`
23			`else mem_cs[2] = 1'b0;`
24			`end`
25
26
27			`always@(*)`
28			`begin`
29			`if(addr_in[15:12] == 4'b1000) mem_cs[3] = 1'b1;`
30			`else mem_cs[3] = 1'b0;`
31			`end`
32
33
34
35
36			`always@(*)`
37			`begin`
38			`if(addr_in[15:14] == 2'b01) mem_cs[4] = 1'b1;`
39			`else mem_cs[4] = 1'b0;`
40			`end`
41
42
43
44
45
46
47
48
49
50
51			`always@(*)`
52			`if ( mem_cs_r[0] ) rdata_out = mem_rdata[7:0];`
53			`else`
54			`if ( mem_cs_r[1] ) rdata_out = mem_rdata[15:8];`
55			`else`
56			`if ( mem_cs_r[2] ) rdata_out = mem_rdata[23:16];`
57			`else`
58			`if ( mem_cs_r[3] ) rdata_out = mem_rdata[31:24];`
59			`else rdata_out = addr_in[0]?mem_rdata[47:40]:mem_rdata[39:32];`
60
61
62
63
64
65			`assign mem_addr = addr_in;`
66			`assign mem_rd = rd_in;`
67			`assign mem_wr = wr_in;`
68			`assign mem_wdata = {wdata_in,wdata_in};`
69			`assign enable = ~(\|mem_wait);`
70
71
72

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [verilog/] [top.body.byte] - Blame information for rev 131