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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_byte.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
micro_bus
byte  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 master_enable
  
  
  
    
      
        enable
        enable
      
    
 
 
 
 
 
 
 
 
 cpu
  
  
  
    
      
        addr
        addr_in
        150
        
      
      
        rdata
        rdata_out
        reg
        70
        
      
 
 
 
      
        wdata
        wdata_in
        70
        
      
 
 
      
        wr
        wr_in
        
      
 
 
      
        rd
        rd_in
        
      
 
 
 
 
    
 
 
 
 
 mem
  
  
  
    
 
      
        addr
        mem_addr
        150
        
      
 
      
        cs
        mem_cs
        reg
        40
        
      
 
      
        wdata
        mem_wdata
        150
        
      
 
      
        rdata
        mem_rdata
        470
        
      
 
 
      
        wait
        mem_wait
        10
        
      
 
 
      
        rd
        mem_rd
        
      
 
      
        wr
        mem_wr
        
      
 
    
 
 
 
 
 
 

 
 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.byte
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body.byte
        verilogSourcefragment
      
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.byte
        verilogSourcemodule
      
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.byte
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 

 
      
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="micro_bus"
                                   spirit:version="byte.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_byte.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`micro_bus`
40			`byte default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71			`master_enable`
72
73
74
75
76
77			`enable`
78			`enable`
79
80
81
82
83
84
85
86
87
88
89			`cpu`
90
91
92
93
94
95			`addr`
96			`addr_in`
97			`150`
98
99
100
101			`rdata`
102			`rdata_out`
103			`reg`
104			`70`
105
106
107
108
109
110
111			`wdata`
112			`wdata_in`
113			`70`
114
115
116
117
118
119			`wr`
120			`wr_in`
121
122
123
124
125
126			`rd`
127			`rd_in`
128
129
130
131
132
133
134
135
136
137
138
139			`mem`
140
141
142
143
144
145
146			`addr`
147			`mem_addr`
148			`150`
149
150
151
152
153			`cs`
154			`mem_cs`
155			`reg`
156			`40`
157
158
159
160
161			`wdata`
162			`mem_wdata`
163			`150`
164
165
166
167
168			`rdata`
169			`mem_rdata`
170			`470`
171
172
173
174
175
176			`wait`
177			`mem_wait`
178			`10`
179
180
181
182
183
184			`rd`
185			`mem_rd`
186
187
188
189
190			`wr`
191			`mem_wr`
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208	133	jt_eaton
209			`elab_verilog`
210			`102.1`
211			`none`
212			`:Simulation:`
213			`./tools/verilog/elab_verilog`
214
215
216			`dest_dir`
217			`io_ports`
218
219
220
221	131	jt_eaton
222
223
224
225
226
227			`gen_verilog`
228			`104.0`
229			`none`
230			`common`
231			`./tools/verilog/gen_verilog`
232
233
234			`destination`
235			`top.byte`
236
237
238			`dest_dir`
239			`../verilog`
240
241
242
243
244
245
246
247
248
249
250
251
252
253			`fs-common`
254
255
256
257			`../verilog/top.body.byte`
258			`verilogSourcefragment`
259
260
261
262
263
264
265
266			`fs-sim`
267
268
269
270			`../verilog/copyright.v`
271			`verilogSourceinclude`
272
273
274
275
276			`../verilog/common/top.byte`
277			`verilogSourcemodule`
278
279
280
281
282
283
284
285
286			`fs-syn`
287
288
289
290			`../verilog/copyright.v`
291			`verilogSourceinclude`
292
293
294
295
296
297			`../verilog/common/top.byte`
298			`verilogSourcemodule`
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319			`Hierarchical`
320
321
322			`spirit:library="logic"`
323			`spirit:name="micro_bus"`
324			`spirit:version="byte.design"/>`
325
326
327
328
329			`verilog`
330
331
332			`spirit:library="Testbench"`
333			`spirit:name="toolflow"`
334			`spirit:version="verilog"/>`
335
336
337
338
339
340
341
342
343			`commoncommon`
344
345			`Verilog`
346
347
348			`fs-common`
349
350
351
352
353			`sim:Simulation:`
354
355			`Verilog`
356
357
358			`fs-sim`
359
360
361
362
363
364
365			`syn:Synthesis:`
366
367			`Verilog`
368
369
370			`fs-syn`
371
372
373
374
375
376			`doc`
377
378
379			`spirit:library="Testbench"`
380			`spirit:name="toolflow"`
381			`spirit:version="documentation"/>`
382
383			`:Documentation:`
384			`Verilog`
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
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406