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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp5.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
micro_bus
exp5  default
 
 
 

 
mb_out
  
  
  
  
  
  
  
  
  
  
 
 
    
 
      
        addr
        
        addr_in
          70
        
      
 
      
        rdata
        
        rdata_out
          150
        
      
 
      
        wdata
        
        wdata_in
          70
        
      
 
      
        rd
        
        rd_in
        
      
 
      
        wr
        
        wr_in
        
      
 
      
        cs
        
        cs_in
        
      
 
      
        wait
        
        wait_out
        reg
        
      
 
    
 
 
 
 
 
 
mas_0
  
  
  
 
    
 
      
        addr
        
        mas_0_addr_out
          30
        
      
 
      
        rdata
        
        mas_0_rdata_in
          70
        
      
 
      
        wdata
        
        mas_0_wdata_out
          70
        
      
 
      
        rd
        
        mas_0_rd_out
        
      
 
      
        wr
        
        mas_0_wr_out
        
      
 
      
        cs
        
        mas_0_cs_out
        
      
 
    
 
 
 
 
 
 
 
 
mas_1
  
  
  
 
    
 
      
        addr
        
        mas_1_addr_out
          30
        
      
 
      
        rdata
        
        mas_1_rdata_in
          70
        
      
 
      
        wdata
        
        mas_1_wdata_out
          70
        
      
 
      
        rd
        
        mas_1_rd_out
        
      
 
      
        wr
        
        mas_1_wr_out
        
      
 
      
        cs
        
        mas_1_cs_out
        
      
 
    
 
 
 
 
 
 
 
 
 
mas_2
  
  
  
 
 
    
 
      
        addr
        
        mas_2_addr_out
          30
        
      
 
      
        rdata
        
        mas_2_rdata_in
          70
        
      
 
      
        wdata
        
        mas_2_wdata_out
          70
        
      
 
      
        rd
        
        mas_2_rd_out
        
      
 
      
        wr
        
        mas_2_wr_out
        
      
 
      
        cs
        
        mas_2_cs_out
        
      
 
    
 
 
 
 
 
 
mas_3
  
  
  
 
    
 
      
        addr
        
        mas_3_addr_out
          30
        
      
 
      
        rdata
        
        mas_3_rdata_in
          70
        
      
 
      
        wdata
        
        mas_3_wdata_out
          70
        
      
 
      
        rd
        
        mas_3_rd_out
        
      
 
      
        wr
        
        mas_3_wr_out
        
      
 
      
        cs
        
        mas_3_cs_out
        
      
 
    
 
 
 
 
 
 
mas_4
  
  
 
  
 
 
    
 
      
        addr
        
        mas_4_addr_out
          30
        
      
 
      
        rdata
        
        mas_4_rdata_in
          70
        
      
 
      
        wdata
        
        mas_4_wdata_out
          70
        
      
 
      
        rd
        
        mas_4_rd_out
        
      
 
      
        wr
        
        mas_4_wr_out
        
      
 
      
        cs
        
        mas_4_cs_out
        
      
 
    
 
 
 
 
 
 

 
 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      exp_default
    
    
      dest_dir
      io_ports
    
  

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.exp5
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body.exp5
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.exp5
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
 
      
        
        ../verilog/common/top.exp5
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 

 
      
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 

 
clk
wire
in

 
 
reset
wire
in

 
 
 
enable
wire
in

 

 
 

 
 
 
 

 
 
   
 
   4
   mb_out
 
 
  
     mas_0
     0x00
   
 
 
  
     mas_1
     0x10
   
 
 
  
     mas_2
     0x20
   
 
 
  
     mas_3
     0x30
   
 
  
     mas_4
     0x40
   
 
 
 
 
 
   
     mas_0
     00
      
       mas_0
       16
       8
     
   
 
   
     mas_1
     10
      
       mas_1
       16
       8
     
   
 
 
   
     mas_2
     20
      
       mas_2
       16
       8
     
   
 
 
 
 
   
     mas_3
     30
      
       mas_3
       16
       8
     
   
 
 
   
     mas_4
     40
      
       mas_4
       16
       8
     
   
 
 
 
 
 
 
   
 
 
 

 
 

 
  
    mas_0
    0x10
    8
  
 
  
    mas_1
    0x10
    8
  
 
  
    mas_2
    0x10
    8
  
 
  
    mas_3
    0x10
    8
  
 
  
    mas_4
    0x10
    8
  
 
 

 
 
 
 

 
 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp5.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`micro_bus`
40			`exp5 default`
41
42
43
44
45
46			`mb_out`
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62			`addr`
63
64			`addr_in`
65			`70`
66
67
68
69
70			`rdata`
71
72			`rdata_out`
73			`150`
74
75
76
77
78			`wdata`
79
80			`wdata_in`
81			`70`
82
83
84
85
86			`rd`
87
88			`rd_in`
89
90
91
92
93			`wr`
94
95			`wr_in`
96
97
98
99
100			`cs`
101
102			`cs_in`
103
104
105
106
107			`wait`
108
109			`wait_out`
110			`reg`
111
112
113
114
115
116
117
118
119
120
121			`mas_0`
122
123
124
125
126
127
128
129			`addr`
130
131			`mas_0_addr_out`
132	133	jt_eaton	`30`
133	131	jt_eaton
134
135
136
137			`rdata`
138
139			`mas_0_rdata_in`
140			`70`
141
142
143
144
145			`wdata`
146
147			`mas_0_wdata_out`
148			`70`
149
150
151
152
153			`rd`
154
155			`mas_0_rd_out`
156
157
158
159
160			`wr`
161
162			`mas_0_wr_out`
163
164
165
166
167			`cs`
168
169			`mas_0_cs_out`
170
171
172
173
174
175
176
177
178
179
180
181
182			`mas_1`
183
184
185
186
187
188
189
190			`addr`
191
192			`mas_1_addr_out`
193	133	jt_eaton	`30`
194	131	jt_eaton
195
196
197
198			`rdata`
199
200			`mas_1_rdata_in`
201			`70`
202
203
204
205
206			`wdata`
207
208			`mas_1_wdata_out`
209			`70`
210
211
212
213
214			`rd`
215
216			`mas_1_rd_out`
217
218
219
220
221			`wr`
222
223			`mas_1_wr_out`
224
225
226
227
228			`cs`
229
230			`mas_1_cs_out`
231
232
233
234
235
236
237
238
239
240
241
242
243
244			`mas_2`
245
246
247
248
249
250
251
252
253			`addr`
254
255			`mas_2_addr_out`
256	133	jt_eaton	`30`
257	131	jt_eaton
258
259
260
261			`rdata`
262
263			`mas_2_rdata_in`
264			`70`
265
266
267
268
269			`wdata`
270
271			`mas_2_wdata_out`
272			`70`
273
274
275
276
277			`rd`
278
279			`mas_2_rd_out`
280
281
282
283
284			`wr`
285
286			`mas_2_wr_out`
287
288
289
290
291			`cs`
292
293			`mas_2_cs_out`
294
295
296
297
298
299
300
301
302
303
304			`mas_3`
305
306
307
308
309
310
311
312			`addr`
313
314			`mas_3_addr_out`
315	133	jt_eaton	`30`
316	131	jt_eaton
317
318
319
320			`rdata`
321
322			`mas_3_rdata_in`
323			`70`
324
325
326
327
328			`wdata`
329
330			`mas_3_wdata_out`
331			`70`
332
333
334
335
336			`rd`
337
338			`mas_3_rd_out`
339
340
341
342
343			`wr`
344
345			`mas_3_wr_out`
346
347
348
349
350			`cs`
351
352			`mas_3_cs_out`
353
354
355
356
357
358
359
360
361
362
363			`mas_4`
364
365
366
367
368
369
370
371
372
373			`addr`
374
375			`mas_4_addr_out`
376	133	jt_eaton	`30`
377	131	jt_eaton
378
379
380
381			`rdata`
382
383			`mas_4_rdata_in`
384			`70`
385
386
387
388
389			`wdata`
390
391			`mas_4_wdata_out`
392			`70`
393
394
395
396
397			`rd`
398
399			`mas_4_rd_out`
400
401
402
403
404			`wr`
405
406			`mas_4_wr_out`
407
408
409
410
411			`cs`
412
413			`mas_4_cs_out`
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432	133	jt_eaton
433			`elab_verilog`
434			`102.1`
435			`none`
436			`:Simulation:`
437			`./tools/verilog/elab_verilog`
438
439
440			`configuration`
441			`exp_default`
442
443
444			`dest_dir`
445			`io_ports`
446
447
448
449	131	jt_eaton
450
451
452			`gen_verilog`
453			`104.0`
454			`none`
455			`common`
456			`./tools/verilog/gen_verilog`
457
458
459			`destination`
460			`top.exp5`
461
462
463			`dest_dir`
464			`../verilog`
465
466
467
468
469
470
471
472
473
474
475
476
477			`fs-common`
478
479
480
481			`../verilog/top.body.exp5`
482			`verilogSourcefragment`
483
484
485
486
487
488			`fs-sim`
489
490
491
492			`../verilog/copyright.v`
493			`verilogSourceinclude`
494
495
496
497
498
499			`../verilog/common/top.exp5`
500			`verilogSourcemodule`
501
502
503
504
505
506
507
508
509
510			`fs-syn`
511
512
513
514			`../verilog/copyright.v`
515			`verilogSourceinclude`
516
517
518
519
520
521
522			`../verilog/common/top.exp5`
523			`verilogSourcemodule`
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547			`verilog`
548
549
550			`spirit:library="Testbench"`
551			`spirit:name="toolflow"`
552			`spirit:version="verilog"/>`
553
554
555
556
557
558
559
560
561			`commoncommon`
562
563			`Verilog`
564
565
566			`fs-common`
567
568
569
570
571			`sim:Simulation:`
572
573			`Verilog`
574
575
576			`fs-sim`
577
578
579
580
581
582			`syn:Synthesis:`
583
584			`Verilog`
585
586
587			`fs-syn`
588
589
590
591
592
593			`doc`
594
595
596			`spirit:library="Testbench"`
597			`spirit:name="toolflow"`
598			`spirit:version="documentation"/>`
599
600			`:Documentation:`
601			`Verilog`
602
603
604
605
606
607
608
609
610
611
612			`clk`
613			`wire`
614			`in`
615
616
617
618			`reset`
619			`wire`
620			`in`
621
622
623
624
625			`enable`
626			`wire`
627			`in`
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643			`4`
644			`mb_out`
645
646
647
648			`mas_0`
649			`0x00`
650
651
652
653
654			`mas_1`
655			`0x10`
656
657
658
659
660			`mas_2`
661			`0x20`
662
663
664
665
666			`mas_3`
667			`0x30`
668
669
670
671			`mas_4`
672			`0x40`
673
674
675
676
677
678
679
680			`mas_0`
681			`00`
682
683			`mas_0`
684			`16`
685			`8`
686
687
688
689
690			`mas_1`
691			`10`
692
693			`mas_1`
694			`16`
695			`8`
696
697
698
699
700
701			`mas_2`
702			`20`
703
704			`mas_2`
705			`16`
706			`8`
707
708
709
710
711
712
713
714			`mas_3`
715			`30`
716
717			`mas_3`
718			`16`
719			`8`
720
721
722
723
724
725			`mas_4`
726			`40`
727
728			`mas_4`
729			`16`
730			`8`
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749			`mas_0`
750			`0x10`
751			`8`
752
753
754
755			`mas_1`
756			`0x10`
757			`8`
758
759
760
761			`mas_2`
762			`0x10`
763			`8`
764
765
766
767			`mas_3`
768			`0x10`
769			`8`
770
771
772
773			`mas_4`
774			`0x10`
775			`8`
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791