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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp6.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
micro_bus
exp6  default
 
 
 

 
mb_out
  
  
  
  
  
  
  
  
  
  
  
 
 
    
 
      
        addr
        
        addr_in
          70
        
      
 
      
        rdata
        
        rdata_out
          150
        
      
 
      
        wdata
        
        wdata_in
          70
        
      
 
      
        rd
        
        rd_in
        
      
 
      
        wr
        
        wr_in
        
      
 
      
        cs
        
        cs_in
        
      
 
      
        wait
        
        wait_out
        reg
        
      
 
    
 
 
 
 
 
 
mas_0
  
  
  
 
    
 
      
        addr
        
        mas_0_addr_out
          70
        
      
 
      
        rdata
        
        mas_0_rdata_in
          70
        
      
 
      
        wdata
        
        mas_0_wdata_out
          70
        
      
 
      
        rd
        
        mas_0_rd_out
        
      
 
      
        wr
        
        mas_0_wr_out
        
      
 
      
        cs
        
        mas_0_cs_out
        
      
 
    
 
 
 
 
 
 
 
 
mas_1
  
  
  
 
    
 
      
        addr
        
        mas_1_addr_out
          70
        
      
 
      
        rdata
        
        mas_1_rdata_in
          70
        
      
 
      
        wdata
        
        mas_1_wdata_out
          70
        
      
 
      
        rd
        
        mas_1_rd_out
        
      
 
      
        wr
        
        mas_1_wr_out
        
      
 
      
        cs
        
        mas_1_cs_out
        
      
 
    
 
 
 
 
 
 
 
 
 
mas_2
  
  
  
 
 
    
 
      
        addr
        
        mas_2_addr_out
          70
        
      
 
      
        rdata
        
        mas_2_rdata_in
          70
        
      
 
      
        wdata
        
        mas_2_wdata_out
          70
        
      
 
      
        rd
        
        mas_2_rd_out
        
      
 
      
        wr
        
        mas_2_wr_out
        
      
 
      
        cs
        
        mas_2_cs_out
        
      
 
    
 
 
 
 
 
 
mas_3
  
  
  
 
    
 
      
        addr
        
        mas_3_addr_out
          70
        
      
 
      
        rdata
        
        mas_3_rdata_in
          70
        
      
 
      
        wdata
        
        mas_3_wdata_out
          70
        
      
 
      
        rd
        
        mas_3_rd_out
        
      
 
      
        wr
        
        mas_3_wr_out
        
      
 
      
        cs
        
        mas_3_cs_out
        
      
 
    
 
 
 
 
 
 
mas_4
  
  
 
  
 
 
    
 
      
        addr
        
        mas_4_addr_out
          70
        
      
 
      
        rdata
        
        mas_4_rdata_in
          70
        
      
 
      
        wdata
        
        mas_4_wdata_out
          70
        
      
 
      
        rd
        
        mas_4_rd_out
        
      
 
      
        wr
        
        mas_4_wr_out
        
      
 
      
        cs
        
        mas_4_cs_out
        
      
 
    
 
 
 
 
 
 
mas_5
  
  
 
  
    
 
      
        addr
        
        mas_5_addr_out
          70
        
      
 
      
        rdata
        
        mas_5_rdata_in
          70
        
      
 
      
        wdata
        
        mas_5_wdata_out
          70
        
      
 
      
        rd
        
        mas_5_rd_out
        
      
 
      
        wr
        
        mas_5_wr_out
        
      
 
      
        cs
        
        mas_5_cs_out
        
      
 
    
 
 
 
 
 

 
 
 

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.exp6
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body.exp6
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.exp6
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
 
      
        
        ../verilog/common/top.exp6
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 

 
      
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 

SLA_ADDR_WIDTH8
SLA_DATA_WIDTH16
MAS_ADDR_WIDTH4
MAS_DATA_WIDTH8

 
 
 

 
clk
wire
in

 
 
reset
wire
in

 
 
 
enable
wire
in

 

 
 

 
 
 
 

 
 
   
 
   4
   mb_out
 
 
  
     mas_0
     0x00
   
 
 
  
     mas_1
     0x10
   
 
 
  
     mas_2
     0x20
   
 
 
  
     mas_3
     0x30
   
 
  
     mas_4
     0x40
   
 
 
  
     mas_5
     0x50
   
 
 
 
   
     mas_0
     00
      
       mas_0
       16
       8
     
   
 
   
     mas_1
     10
      
       mas_1
       16
       8
     
   
 
 
   
     mas_2
     20
      
       mas_2
       16
       8
     
   
 
 
 
 
   
     mas_3
     30
      
       mas_3
       16
       8
     
   
 
 
   
     mas_4
     40
      
       mas_4
       16
       8
     
   
 
 
   
     mas_5
     50
      
       mas_5
       16
       8
     
   
 
 
 
 
 
   
 
 
 

 
 

 
  
    mas_0
    0x10
    8
  
 
  
    mas_1
    0x10
    8
  
 
  
    mas_2
    0x10
    8
  
 
  
    mas_3
    0x10
    8
  
 
  
    mas_4
    0x10
    8
  
 
  
    mas_5
    0x10
    8
  
 
 

 
 
 
 

 
 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp6.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`micro_bus`
40			`exp6 default`
41
42
43
44
45
46			`mb_out`
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63			`addr`
64
65			`addr_in`
66			`70`
67
68
69
70
71			`rdata`
72
73			`rdata_out`
74			`150`
75
76
77
78
79			`wdata`
80
81			`wdata_in`
82			`70`
83
84
85
86
87			`rd`
88
89			`rd_in`
90
91
92
93
94			`wr`
95
96			`wr_in`
97
98
99
100
101			`cs`
102
103			`cs_in`
104
105
106
107
108			`wait`
109
110			`wait_out`
111			`reg`
112
113
114
115
116
117
118
119
120
121
122			`mas_0`
123
124
125
126
127
128
129
130			`addr`
131
132			`mas_0_addr_out`
133			`70`
134
135
136
137
138			`rdata`
139
140			`mas_0_rdata_in`
141			`70`
142
143
144
145
146			`wdata`
147
148			`mas_0_wdata_out`
149			`70`
150
151
152
153
154			`rd`
155
156			`mas_0_rd_out`
157
158
159
160
161			`wr`
162
163			`mas_0_wr_out`
164
165
166
167
168			`cs`
169
170			`mas_0_cs_out`
171
172
173
174
175
176
177
178
179
180
181
182
183			`mas_1`
184
185
186
187
188
189
190
191			`addr`
192
193			`mas_1_addr_out`
194			`70`
195
196
197
198
199			`rdata`
200
201			`mas_1_rdata_in`
202			`70`
203
204
205
206
207			`wdata`
208
209			`mas_1_wdata_out`
210			`70`
211
212
213
214
215			`rd`
216
217			`mas_1_rd_out`
218
219
220
221
222			`wr`
223
224			`mas_1_wr_out`
225
226
227
228
229			`cs`
230
231			`mas_1_cs_out`
232
233
234
235
236
237
238
239
240
241
242
243
244
245			`mas_2`
246
247
248
249
250
251
252
253
254			`addr`
255
256			`mas_2_addr_out`
257			`70`
258
259
260
261
262			`rdata`
263
264			`mas_2_rdata_in`
265			`70`
266
267
268
269
270			`wdata`
271
272			`mas_2_wdata_out`
273			`70`
274
275
276
277
278			`rd`
279
280			`mas_2_rd_out`
281
282
283
284
285			`wr`
286
287			`mas_2_wr_out`
288
289
290
291
292			`cs`
293
294			`mas_2_cs_out`
295
296
297
298
299
300
301
302
303
304
305			`mas_3`
306
307
308
309
310
311
312
313			`addr`
314
315			`mas_3_addr_out`
316			`70`
317
318
319
320
321			`rdata`
322
323			`mas_3_rdata_in`
324			`70`
325
326
327
328
329			`wdata`
330
331			`mas_3_wdata_out`
332			`70`
333
334
335
336
337			`rd`
338
339			`mas_3_rd_out`
340
341
342
343
344			`wr`
345
346			`mas_3_wr_out`
347
348
349
350
351			`cs`
352
353			`mas_3_cs_out`
354
355
356
357
358
359
360
361
362
363
364			`mas_4`
365
366
367
368
369
370
371
372
373
374			`addr`
375
376			`mas_4_addr_out`
377			`70`
378
379
380
381
382			`rdata`
383
384			`mas_4_rdata_in`
385			`70`
386
387
388
389
390			`wdata`
391
392			`mas_4_wdata_out`
393			`70`
394
395
396
397
398			`rd`
399
400			`mas_4_rd_out`
401
402
403
404
405			`wr`
406
407			`mas_4_wr_out`
408
409
410
411
412			`cs`
413
414			`mas_4_cs_out`
415
416
417
418
419
420
421
422
423
424
425			`mas_5`
426
427
428
429
430
431
432
433			`addr`
434
435			`mas_5_addr_out`
436			`70`
437
438
439
440
441			`rdata`
442
443			`mas_5_rdata_in`
444			`70`
445
446
447
448
449			`wdata`
450
451			`mas_5_wdata_out`
452			`70`
453
454
455
456
457			`rd`
458
459			`mas_5_rd_out`
460
461
462
463
464			`wr`
465
466			`mas_5_wr_out`
467
468
469
470
471			`cs`
472
473			`mas_5_cs_out`
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496			`gen_verilog`
497			`104.0`
498			`none`
499			`common`
500			`./tools/verilog/gen_verilog`
501
502
503			`destination`
504			`top.exp6`
505
506
507			`dest_dir`
508			`../verilog`
509
510
511
512
513
514
515
516
517
518
519
520
521			`fs-common`
522
523
524
525			`../verilog/top.body.exp6`
526			`verilogSourcefragment`
527
528
529
530
531
532			`fs-sim`
533
534
535
536			`../verilog/copyright.v`
537			`verilogSourceinclude`
538
539
540
541
542
543			`../verilog/common/top.exp6`
544			`verilogSourcemodule`
545
546
547
548
549
550
551
552
553
554			`fs-syn`
555
556
557
558			`../verilog/copyright.v`
559			`verilogSourceinclude`
560
561
562
563
564
565
566			`../verilog/common/top.exp6`
567			`verilogSourcemodule`
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591			`verilog`
592
593
594			`spirit:library="Testbench"`
595			`spirit:name="toolflow"`
596			`spirit:version="verilog"/>`
597
598
599
600
601
602
603
604
605			`commoncommon`
606
607			`Verilog`
608
609
610			`fs-common`
611
612
613
614
615			`sim:Simulation:`
616
617			`Verilog`
618
619
620			`fs-sim`
621
622
623
624
625
626			`syn:Synthesis:`
627
628			`Verilog`
629
630
631			`fs-syn`
632
633
634
635
636
637			`doc`
638
639
640			`spirit:library="Testbench"`
641			`spirit:name="toolflow"`
642			`spirit:version="documentation"/>`
643
644			`:Documentation:`
645			`Verilog`
646
647
648
649
650
651
652
653
654
655			`SLA_ADDR_WIDTH8`
656			`SLA_DATA_WIDTH16`
657			`MAS_ADDR_WIDTH4`
658			`MAS_DATA_WIDTH8`
659
660
661
662
663
664
665			`clk`
666			`wire`
667			`in`
668
669
670
671			`reset`
672			`wire`
673			`in`
674
675
676
677
678			`enable`
679			`wire`
680			`in`
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696			`4`
697			`mb_out`
698
699
700
701			`mas_0`
702			`0x00`
703
704
705
706
707			`mas_1`
708			`0x10`
709
710
711
712
713			`mas_2`
714			`0x20`
715
716
717
718
719			`mas_3`
720			`0x30`
721
722
723
724			`mas_4`
725			`0x40`
726
727
728
729
730			`mas_5`
731			`0x50`
732
733
734
735
736
737			`mas_0`
738			`00`
739
740			`mas_0`
741			`16`
742			`8`
743
744
745
746
747			`mas_1`
748			`10`
749
750			`mas_1`
751			`16`
752			`8`
753
754
755
756
757
758			`mas_2`
759			`20`
760
761			`mas_2`
762			`16`
763			`8`
764
765
766
767
768
769
770
771			`mas_3`
772			`30`
773
774			`mas_3`
775			`16`
776			`8`
777
778
779
780
781
782			`mas_4`
783			`40`
784
785			`mas_4`
786			`16`
787			`8`
788
789
790
791
792
793			`mas_5`
794			`50`
795
796			`mas_5`
797			`16`
798			`8`
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816			`mas_0`
817			`0x10`
818			`8`
819
820
821
822			`mas_1`
823			`0x10`
824			`8`
825
826
827
828			`mas_2`
829			`0x10`
830			`8`
831
832
833
834			`mas_3`
835			`0x10`
836			`8`
837
838
839
840			`mas_4`
841			`0x10`
842			`8`
843
844
845
846			`mas_5`
847			`0x10`
848			`8`
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864