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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp6.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
micro_bus
exp6  default
 
 
 

 
mb_out
  
  
  
  
  
  
  
  
  
  
  
 
 
    
 
      
        addr
        
        addr_in
          70
        
      
 
      
        rdata
        
        rdata_out
          150
        
      
 
      
        wdata
        
        wdata_in
          70
        
      
 
      
        rd
        
        rd_in
        
      
 
      
        wr
        
        wr_in
        
      
 
      
        cs
        
        cs_in
        
      
 
      
        wait
        
        wait_out
        reg
        
      
 
    
 
 
 
 
 
 
mas_0
  
  
  
 
    
 
      
        addr
        
        mas_0_addr_out
          30
        
      
 
      
        rdata
        
        mas_0_rdata_in
          70
        
      
 
      
        wdata
        
        mas_0_wdata_out
          70
        
      
 
      
        rd
        
        mas_0_rd_out
        
      
 
      
        wr
        
        mas_0_wr_out
        
      
 
      
        cs
        
        mas_0_cs_out
        
      
 
    
 
 
 
 
 
 
 
 
mas_1
  
  
  
 
    
 
      
        addr
        
        mas_1_addr_out
          30
        
      
 
      
        rdata
        
        mas_1_rdata_in
          70
        
      
 
      
        wdata
        
        mas_1_wdata_out
          70
        
      
 
      
        rd
        
        mas_1_rd_out
        
      
 
      
        wr
        
        mas_1_wr_out
        
      
 
      
        cs
        
        mas_1_cs_out
        
      
 
    
 
 
 
 
 
 
 
 
 
mas_2
  
  
  
 
 
    
 
      
        addr
        
        mas_2_addr_out
          30
        
      
 
      
        rdata
        
        mas_2_rdata_in
          70
        
      
 
      
        wdata
        
        mas_2_wdata_out
          70
        
      
 
      
        rd
        
        mas_2_rd_out
        
      
 
      
        wr
        
        mas_2_wr_out
        
      
 
      
        cs
        
        mas_2_cs_out
        
      
 
    
 
 
 
 
 
 
mas_3
  
  
  
 
    
 
      
        addr
        
        mas_3_addr_out
          30
        
      
 
      
        rdata
        
        mas_3_rdata_in
          70
        
      
 
      
        wdata
        
        mas_3_wdata_out
          70
        
      
 
      
        rd
        
        mas_3_rd_out
        
      
 
      
        wr
        
        mas_3_wr_out
        
      
 
      
        cs
        
        mas_3_cs_out
        
      
 
    
 
 
 
 
 
 
mas_4
  
  
 
  
 
 
    
 
      
        addr
        
        mas_4_addr_out
          30
        
      
 
      
        rdata
        
        mas_4_rdata_in
          70
        
      
 
      
        wdata
        
        mas_4_wdata_out
          70
        
      
 
      
        rd
        
        mas_4_rd_out
        
      
 
      
        wr
        
        mas_4_wr_out
        
      
 
      
        cs
        
        mas_4_cs_out
        
      
 
    
 
 
 
 
 
 
mas_5
  
  
 
  
    
 
      
        addr
        
        mas_5_addr_out
          30
        
      
 
      
        rdata
        
        mas_5_rdata_in
          70
        
      
 
      
        wdata
        
        mas_5_wdata_out
          70
        
      
 
      
        rd
        
        mas_5_rd_out
        
      
 
      
        wr
        
        mas_5_wr_out
        
      
 
      
        cs
        
        mas_5_cs_out
        
      
 
    
 
 
 
 
 

 
 
 

 
 
 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      exp_default
    
    
      dest_dir
      io_ports
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.exp6
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body.exp6
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.exp6
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
 
      
        
        ../verilog/common/top.exp6
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 

 
      
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 
 
 

 
clk
wire
in

 
 
reset
wire
in

 
 
 
enable
wire
in

 

 
 

 
 
 
 

 
 
   
 
   4
   mb_out
 
 
  
     mas_0
     0x00
   
 
 
  
     mas_1
     0x10
   
 
 
  
     mas_2
     0x20
   
 
 
  
     mas_3
     0x30
   
 
  
     mas_4
     0x40
   
 
 
  
     mas_5
     0x50
   
 
 
 
   
     mas_0
     00
      
       mas_0
       16
       8
     
   
 
   
     mas_1
     10
      
       mas_1
       16
       8
     
   
 
 
   
     mas_2
     20
      
       mas_2
       16
       8
     
   
 
 
 
 
   
     mas_3
     30
      
       mas_3
       16
       8
     
   
 
 
   
     mas_4
     40
      
       mas_4
       16
       8
     
   
 
 
   
     mas_5
     50
      
       mas_5
       16
       8
     
   
 
 
 
 
 
   
 
 
 

 
 

 
  
    mas_0
    0x10
    8
  
 
  
    mas_1
    0x10
    8
  
 
  
    mas_2
    0x10
    8
  
 
  
    mas_3
    0x10
    8
  
 
  
    mas_4
    0x10
    8
  
 
  
    mas_5
    0x10
    8
  
 
 

 
 
 
 

 
 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp6.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`micro_bus`
40			`exp6 default`
41
42
43
44
45
46			`mb_out`
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63			`addr`
64
65			`addr_in`
66			`70`
67
68
69
70
71			`rdata`
72
73			`rdata_out`
74			`150`
75
76
77
78
79			`wdata`
80
81			`wdata_in`
82			`70`
83
84
85
86
87			`rd`
88
89			`rd_in`
90
91
92
93
94			`wr`
95
96			`wr_in`
97
98
99
100
101			`cs`
102
103			`cs_in`
104
105
106
107
108			`wait`
109
110			`wait_out`
111			`reg`
112
113
114
115
116
117
118
119
120
121
122			`mas_0`
123
124
125
126
127
128
129
130			`addr`
131
132			`mas_0_addr_out`
133	133	jt_eaton	`30`
134	131	jt_eaton
135
136
137
138			`rdata`
139
140			`mas_0_rdata_in`
141			`70`
142
143
144
145
146			`wdata`
147
148			`mas_0_wdata_out`
149			`70`
150
151
152
153
154			`rd`
155
156			`mas_0_rd_out`
157
158
159
160
161			`wr`
162
163			`mas_0_wr_out`
164
165
166
167
168			`cs`
169
170			`mas_0_cs_out`
171
172
173
174
175
176
177
178
179
180
181
182
183			`mas_1`
184
185
186
187
188
189
190
191			`addr`
192
193			`mas_1_addr_out`
194	133	jt_eaton	`30`
195	131	jt_eaton
196
197
198
199			`rdata`
200
201			`mas_1_rdata_in`
202			`70`
203
204
205
206
207			`wdata`
208
209			`mas_1_wdata_out`
210			`70`
211
212
213
214
215			`rd`
216
217			`mas_1_rd_out`
218
219
220
221
222			`wr`
223
224			`mas_1_wr_out`
225
226
227
228
229			`cs`
230
231			`mas_1_cs_out`
232
233
234
235
236
237
238
239
240
241
242
243
244
245			`mas_2`
246
247
248
249
250
251
252
253
254			`addr`
255
256			`mas_2_addr_out`
257	133	jt_eaton	`30`
258	131	jt_eaton
259
260
261
262			`rdata`
263
264			`mas_2_rdata_in`
265			`70`
266
267
268
269
270			`wdata`
271
272			`mas_2_wdata_out`
273			`70`
274
275
276
277
278			`rd`
279
280			`mas_2_rd_out`
281
282
283
284
285			`wr`
286
287			`mas_2_wr_out`
288
289
290
291
292			`cs`
293
294			`mas_2_cs_out`
295
296
297
298
299
300
301
302
303
304
305			`mas_3`
306
307
308
309
310
311
312
313			`addr`
314
315			`mas_3_addr_out`
316	133	jt_eaton	`30`
317	131	jt_eaton
318
319
320
321			`rdata`
322
323			`mas_3_rdata_in`
324			`70`
325
326
327
328
329			`wdata`
330
331			`mas_3_wdata_out`
332			`70`
333
334
335
336
337			`rd`
338
339			`mas_3_rd_out`
340
341
342
343
344			`wr`
345
346			`mas_3_wr_out`
347
348
349
350
351			`cs`
352
353			`mas_3_cs_out`
354
355
356
357
358
359
360
361
362
363
364			`mas_4`
365
366
367
368
369
370
371
372
373
374			`addr`
375
376			`mas_4_addr_out`
377	133	jt_eaton	`30`
378	131	jt_eaton
379
380
381
382			`rdata`
383
384			`mas_4_rdata_in`
385			`70`
386
387
388
389
390			`wdata`
391
392			`mas_4_wdata_out`
393			`70`
394
395
396
397
398			`rd`
399
400			`mas_4_rd_out`
401
402
403
404
405			`wr`
406
407			`mas_4_wr_out`
408
409
410
411
412			`cs`
413
414			`mas_4_cs_out`
415
416
417
418
419
420
421
422
423
424
425			`mas_5`
426
427
428
429
430
431
432
433			`addr`
434
435			`mas_5_addr_out`
436	133	jt_eaton	`30`
437	131	jt_eaton
438
439
440
441			`rdata`
442
443			`mas_5_rdata_in`
444			`70`
445
446
447
448
449			`wdata`
450
451			`mas_5_wdata_out`
452			`70`
453
454
455
456
457			`rd`
458
459			`mas_5_rd_out`
460
461
462
463
464			`wr`
465
466			`mas_5_wr_out`
467
468
469
470
471			`cs`
472
473			`mas_5_cs_out`
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494	133	jt_eaton
495			`elab_verilog`
496			`102.1`
497			`none`
498			`:Simulation:`
499			`./tools/verilog/elab_verilog`
500
501
502			`configuration`
503			`exp_default`
504
505
506			`dest_dir`
507			`io_ports`
508
509
510
511	131	jt_eaton
512	133	jt_eaton
513
514	131	jt_eaton
515			`gen_verilog`
516			`104.0`
517			`none`
518			`common`
519			`./tools/verilog/gen_verilog`
520
521
522			`destination`
523			`top.exp6`
524
525
526			`dest_dir`
527			`../verilog`
528
529
530
531
532
533
534
535
536
537
538
539
540			`fs-common`
541
542
543
544			`../verilog/top.body.exp6`
545			`verilogSourcefragment`
546
547
548
549
550
551			`fs-sim`
552
553
554
555			`../verilog/copyright.v`
556			`verilogSourceinclude`
557
558
559
560
561
562			`../verilog/common/top.exp6`
563			`verilogSourcemodule`
564
565
566
567
568
569
570
571
572
573			`fs-syn`
574
575
576
577			`../verilog/copyright.v`
578			`verilogSourceinclude`
579
580
581
582
583
584
585			`../verilog/common/top.exp6`
586			`verilogSourcemodule`
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610			`verilog`
611
612
613			`spirit:library="Testbench"`
614			`spirit:name="toolflow"`
615			`spirit:version="verilog"/>`
616
617
618
619
620
621
622
623
624			`commoncommon`
625
626			`Verilog`
627
628
629			`fs-common`
630
631
632
633
634			`sim:Simulation:`
635
636			`Verilog`
637
638
639			`fs-sim`
640
641
642
643
644
645			`syn:Synthesis:`
646
647			`Verilog`
648
649
650			`fs-syn`
651
652
653
654
655
656			`doc`
657
658
659			`spirit:library="Testbench"`
660			`spirit:name="toolflow"`
661			`spirit:version="documentation"/>`
662
663			`:Documentation:`
664			`Verilog`
665
666
667
668
669
670
671
672
673
674
675
676
677			`clk`
678			`wire`
679			`in`
680
681
682
683			`reset`
684			`wire`
685			`in`
686
687
688
689
690			`enable`
691			`wire`
692			`in`
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708			`4`
709			`mb_out`
710
711
712
713			`mas_0`
714			`0x00`
715
716
717
718
719			`mas_1`
720			`0x10`
721
722
723
724
725			`mas_2`
726			`0x20`
727
728
729
730
731			`mas_3`
732			`0x30`
733
734
735
736			`mas_4`
737			`0x40`
738
739
740
741
742			`mas_5`
743			`0x50`
744
745
746
747
748
749			`mas_0`
750			`00`
751
752			`mas_0`
753			`16`
754			`8`
755
756
757
758
759			`mas_1`
760			`10`
761
762			`mas_1`
763			`16`
764			`8`
765
766
767
768
769
770			`mas_2`
771			`20`
772
773			`mas_2`
774			`16`
775			`8`
776
777
778
779
780
781
782
783			`mas_3`
784			`30`
785
786			`mas_3`
787			`16`
788			`8`
789
790
791
792
793
794			`mas_4`
795			`40`
796
797			`mas_4`
798			`16`
799			`8`
800
801
802
803
804
805			`mas_5`
806			`50`
807
808			`mas_5`
809			`16`
810			`8`
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828			`mas_0`
829			`0x10`
830			`8`
831
832
833
834			`mas_1`
835			`0x10`
836			`8`
837
838
839
840			`mas_2`
841			`0x10`
842			`8`
843
844
845
846			`mas_3`
847			`0x10`
848			`8`
849
850
851
852			`mas_4`
853			`0x10`
854			`8`
855
856
857
858			`mas_5`
859			`0x10`
860			`8`
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876