URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp9.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
micro_bus
exp9  default
 
 
 

 
mb_out
  
  
  
  
  
  
  
  
  
  
  
  
  
  
 
 
    
 
      
        addr
        
        addr_in
          70
        
      
 
      
        rdata
        
        rdata_out
          150
        
      
 
      
        wdata
        
        wdata_in
          70
        
      
 
      
        rd
        
        rd_in
        
      
 
      
        wr
        
        wr_in
        
      
 
      
        cs
        
        cs_in
        
      
 
      
        wait
        
        wait_out
        reg
        
      
 
    
 
 
 
 
 
 
mas_0
  
  
  
 
    
 
      
        addr
        
        mas_0_addr_out
          30
        
      
 
      
        rdata
        
        mas_0_rdata_in
          70
        
      
 
      
        wdata
        
        mas_0_wdata_out
          70
        
      
 
      
        rd
        
        mas_0_rd_out
        
      
 
      
        wr
        
        mas_0_wr_out
        
      
 
      
        cs
        
        mas_0_cs_out
        
      
 
    
 
 
 
 
 
 
 
 
mas_1
  
  
  
 
    
 
      
        addr
        
        mas_1_addr_out
          30
        
      
 
      
        rdata
        
        mas_1_rdata_in
          70
        
      
 
      
        wdata
        
        mas_1_wdata_out
          70
        
      
 
      
        rd
        
        mas_1_rd_out
        
      
 
      
        wr
        
        mas_1_wr_out
        
      
 
      
        cs
        
        mas_1_cs_out
        
      
 
    
 
 
 
 
 
 
 
 
 
mas_2
  
  
  
 
 
    
 
      
        addr
        
        mas_2_addr_out
          30
        
      
 
      
        rdata
        
        mas_2_rdata_in
          70
        
      
 
      
        wdata
        
        mas_2_wdata_out
          70
        
      
 
      
        rd
        
        mas_2_rd_out
        
      
 
      
        wr
        
        mas_2_wr_out
        
      
 
      
        cs
        
        mas_2_cs_out
        
      
 
    
 
 
 
 
 
 
mas_3
  
  
  
 
    
 
      
        addr
        
        mas_3_addr_out
          30
        
      
 
      
        rdata
        
        mas_3_rdata_in
          70
        
      
 
      
        wdata
        
        mas_3_wdata_out
          70
        
      
 
      
        rd
        
        mas_3_rd_out
        
      
 
      
        wr
        
        mas_3_wr_out
        
      
 
      
        cs
        
        mas_3_cs_out
        
      
 
    
 
 
 
 
 
 
mas_4
  
  
 
  
 
 
    
 
      
        addr
        
        mas_4_addr_out
          30
        
      
 
      
        rdata
        
        mas_4_rdata_in
          70
        
      
 
      
        wdata
        
        mas_4_wdata_out
          70
        
      
 
      
        rd
        
        mas_4_rd_out
        
      
 
      
        wr
        
        mas_4_wr_out
        
      
 
      
        cs
        
        mas_4_cs_out
        
      
 
    
 
 
 
 
 
 
mas_5
  
  
 
  
    
 
      
        addr
        
        mas_5_addr_out
          30
        
      
 
      
        rdata
        
        mas_5_rdata_in
          70
        
      
 
      
        wdata
        
        mas_5_wdata_out
          70
        
      
 
      
        rd
        
        mas_5_rd_out
        
      
 
      
        wr
        
        mas_5_wr_out
        
      
 
      
        cs
        
        mas_5_cs_out
        
      
 
    
 
 
 
 
 
 
mas_6
  
  
 
  
 
    
 
      
        addr
        
        mas_6_addr_out
          30
        
      
 
      
        rdata
        
        mas_6_rdata_in
          70
        
      
 
      
        wdata
        
        mas_6_wdata_out
          70
        
      
 
      
        rd
        
        mas_6_rd_out
        
      
 
      
        wr
        
        mas_6_wr_out
        
      
 
      
        cs
        
        mas_6_cs_out
        
      
 
    
 
 
 
 
 
 
mas_7
  
  
 
  
 
 
    
 
      
        addr
        
        mas_7_addr_out
          30
        
      
 
      
        rdata
        
        mas_7_rdata_in
          70
        
      
 
      
        wdata
        
        mas_7_wdata_out
          70
        
      
 
      
        rd
        
        mas_7_rd_out
        
      
 
      
        wr
        
        mas_7_wr_out
        
      
 
      
        cs
        
        mas_7_cs_out
        
      
 
    
 
 
 
 
 
 
mas_8
  
  
 
  
 
    
 
      
        addr
        
        mas_8_addr_out
          30
        
      
 
      
        rdata
        
        mas_8_rdata_in
          70
        
      
 
      
        wdata
        
        mas_8_wdata_out
          70
        
      
 
      
        rd
        
        mas_8_rd_out
        
      
 
      
        wr
        
        mas_8_wr_out
        
      
 
      
        cs
        
        mas_8_cs_out
        
      
 
    
 
 
 
 
 
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      micro_bus_exp9
    
  

 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body.exp9
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/micro_bus_exp9
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
 
      
        
        ../verilog/common/micro_bus_exp9
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 

 
      
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 
 

 
clk
wire
in

 
 
reset
wire
in

 
 
 
enable
wire
in

 

 
 

 
 
 
 

 
 
   
 
   4
   mb_out
 
 
  
     mas_0
     0x00
   
 
 
  
     mas_1
     0x10
   
 
 
  
     mas_2
     0x20
   
 
 
  
     mas_3
     0x30
   
 
  
     mas_4
     0x40
   
 
 
  
     mas_5
     0x50
   
 
 
  
     mas_6
     0x60
   
 
 
  
     mas_7
     0x70
   
 
 
  
     mas_8
     0x80
   
 
 
   
 
 
 

 
 

 
  
    mas_0
    0x10
    8
  
 
  
    mas_1
    0x10
    8
  
 
  
    mas_2
    0x10
    8
  
 
  
    mas_3
    0x10
    8
  
 
  
    mas_4
    0x10
    8
  
 
  
    mas_5
    0x10
    8
  
 
  
    mas_6
    0x10
    8
  
 
  
    mas_7
    0x10
    8
  
 
  
    mas_8
    0x10
    8
  
 
 
 
 
 
 

 
 
 
 

 
 
 
 
 
 
 

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp9.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`micro_bus`
40			`exp9 default`
41
42
43
44
45
46			`mb_out`
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66			`addr`
67
68			`addr_in`
69			`70`
70
71
72
73
74			`rdata`
75
76			`rdata_out`
77			`150`
78
79
80
81
82			`wdata`
83
84			`wdata_in`
85			`70`
86
87
88
89
90			`rd`
91
92			`rd_in`
93
94
95
96
97			`wr`
98
99			`wr_in`
100
101
102
103
104			`cs`
105
106			`cs_in`
107
108
109
110
111			`wait`
112
113			`wait_out`
114			`reg`
115
116
117
118
119
120
121
122
123
124
125			`mas_0`
126
127
128
129
130
131
132
133			`addr`
134
135			`mas_0_addr_out`
136	133	jt_eaton	`30`
137	131	jt_eaton
138
139
140
141			`rdata`
142
143			`mas_0_rdata_in`
144			`70`
145
146
147
148
149			`wdata`
150
151			`mas_0_wdata_out`
152			`70`
153
154
155
156
157			`rd`
158
159			`mas_0_rd_out`
160
161
162
163
164			`wr`
165
166			`mas_0_wr_out`
167
168
169
170
171			`cs`
172
173			`mas_0_cs_out`
174
175
176
177
178
179
180
181
182
183
184
185
186			`mas_1`
187
188
189
190
191
192
193
194			`addr`
195
196			`mas_1_addr_out`
197	133	jt_eaton	`30`
198	131	jt_eaton
199
200
201
202			`rdata`
203
204			`mas_1_rdata_in`
205			`70`
206
207
208
209
210			`wdata`
211
212			`mas_1_wdata_out`
213			`70`
214
215
216
217
218			`rd`
219
220			`mas_1_rd_out`
221
222
223
224
225			`wr`
226
227			`mas_1_wr_out`
228
229
230
231
232			`cs`
233
234			`mas_1_cs_out`
235
236
237
238
239
240
241
242
243
244
245
246
247
248			`mas_2`
249
250
251
252
253
254
255
256
257			`addr`
258
259			`mas_2_addr_out`
260	133	jt_eaton	`30`
261	131	jt_eaton
262
263
264
265			`rdata`
266
267			`mas_2_rdata_in`
268			`70`
269
270
271
272
273			`wdata`
274
275			`mas_2_wdata_out`
276			`70`
277
278
279
280
281			`rd`
282
283			`mas_2_rd_out`
284
285
286
287
288			`wr`
289
290			`mas_2_wr_out`
291
292
293
294
295			`cs`
296
297			`mas_2_cs_out`
298
299
300
301
302
303
304
305
306
307
308			`mas_3`
309
310
311
312
313
314
315
316			`addr`
317
318			`mas_3_addr_out`
319	133	jt_eaton	`30`
320	131	jt_eaton
321
322
323
324			`rdata`
325
326			`mas_3_rdata_in`
327			`70`
328
329
330
331
332			`wdata`
333
334			`mas_3_wdata_out`
335			`70`
336
337
338
339
340			`rd`
341
342			`mas_3_rd_out`
343
344
345
346
347			`wr`
348
349			`mas_3_wr_out`
350
351
352
353
354			`cs`
355
356			`mas_3_cs_out`
357
358
359
360
361
362
363
364
365
366
367			`mas_4`
368
369
370
371
372
373
374
375
376
377			`addr`
378
379			`mas_4_addr_out`
380	133	jt_eaton	`30`
381	131	jt_eaton
382
383
384
385			`rdata`
386
387			`mas_4_rdata_in`
388			`70`
389
390
391
392
393			`wdata`
394
395			`mas_4_wdata_out`
396			`70`
397
398
399
400
401			`rd`
402
403			`mas_4_rd_out`
404
405
406
407
408			`wr`
409
410			`mas_4_wr_out`
411
412
413
414
415			`cs`
416
417			`mas_4_cs_out`
418
419
420
421
422
423
424
425
426
427
428			`mas_5`
429
430
431
432
433
434
435
436			`addr`
437
438			`mas_5_addr_out`
439	133	jt_eaton	`30`
440	131	jt_eaton
441
442
443
444			`rdata`
445
446			`mas_5_rdata_in`
447			`70`
448
449
450
451
452			`wdata`
453
454			`mas_5_wdata_out`
455			`70`
456
457
458
459
460			`rd`
461
462			`mas_5_rd_out`
463
464
465
466
467			`wr`
468
469			`mas_5_wr_out`
470
471
472
473
474			`cs`
475
476			`mas_5_cs_out`
477
478
479
480
481
482
483
484
485
486
487			`mas_6`
488
489
490
491
492
493
494
495
496			`addr`
497
498			`mas_6_addr_out`
499	133	jt_eaton	`30`
500	131	jt_eaton
501
502
503
504			`rdata`
505
506			`mas_6_rdata_in`
507			`70`
508
509
510
511
512			`wdata`
513
514			`mas_6_wdata_out`
515			`70`
516
517
518
519
520			`rd`
521
522			`mas_6_rd_out`
523
524
525
526
527			`wr`
528
529			`mas_6_wr_out`
530
531
532
533
534			`cs`
535
536			`mas_6_cs_out`
537
538
539
540
541
542
543
544
545
546
547			`mas_7`
548
549
550
551
552
553
554
555
556
557			`addr`
558
559			`mas_7_addr_out`
560	133	jt_eaton	`30`
561	131	jt_eaton
562
563
564
565			`rdata`
566
567			`mas_7_rdata_in`
568			`70`
569
570
571
572
573			`wdata`
574
575			`mas_7_wdata_out`
576			`70`
577
578
579
580
581			`rd`
582
583			`mas_7_rd_out`
584
585
586
587
588			`wr`
589
590			`mas_7_wr_out`
591
592
593
594
595			`cs`
596
597			`mas_7_cs_out`
598
599
600
601
602
603
604
605
606
607
608			`mas_8`
609
610
611
612
613
614
615
616
617			`addr`
618
619			`mas_8_addr_out`
620	133	jt_eaton	`30`
621	131	jt_eaton
622
623
624
625			`rdata`
626
627			`mas_8_rdata_in`
628			`70`
629
630
631
632
633			`wdata`
634
635			`mas_8_wdata_out`
636			`70`
637
638
639
640
641			`rd`
642
643			`mas_8_rd_out`
644
645
646
647
648			`wr`
649
650			`mas_8_wr_out`
651
652
653
654
655			`cs`
656
657			`mas_8_cs_out`
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686			`gen_verilog`
687			`104.0`
688			`none`
689			`common`
690			`./tools/verilog/gen_verilog`
691
692
693			`destination`
694	134	jt_eaton	`micro_bus_exp9`
695	131	jt_eaton
696
697
698
699
700
701
702
703
704
705
706
707			`fs-common`
708
709
710
711			`../verilog/top.body.exp9`
712			`verilogSourcefragment`
713
714
715
716
717
718			`fs-sim`
719
720
721
722			`../verilog/copyright.v`
723			`verilogSourceinclude`
724
725
726
727
728
729	134	jt_eaton	`../verilog/common/micro_bus_exp9`
730	131	jt_eaton	`verilogSourcemodule`
731
732
733
734
735
736
737
738
739
740			`fs-syn`
741
742
743
744			`../verilog/copyright.v`
745			`verilogSourceinclude`
746
747
748
749
750
751
752	134	jt_eaton	`../verilog/common/micro_bus_exp9`
753	131	jt_eaton	`verilogSourcemodule`
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777			`verilog`
778
779
780			`spirit:library="Testbench"`
781			`spirit:name="toolflow"`
782			`spirit:version="verilog"/>`
783
784
785
786
787
788
789
790
791			`commoncommon`
792
793			`Verilog`
794
795
796			`fs-common`
797
798
799
800
801			`sim:Simulation:`
802
803			`Verilog`
804
805
806			`fs-sim`
807
808
809
810
811
812			`syn:Synthesis:`
813
814			`Verilog`
815
816
817			`fs-syn`
818
819
820
821
822
823			`doc`
824
825
826			`spirit:library="Testbench"`
827			`spirit:name="toolflow"`
828			`spirit:version="documentation"/>`
829
830			`:Documentation:`
831			`Verilog`
832
833
834
835
836
837
838
839
840
841
842
843			`clk`
844			`wire`
845			`in`
846
847
848
849			`reset`
850			`wire`
851			`in`
852
853
854
855
856			`enable`
857			`wire`
858			`in`
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874			`4`
875			`mb_out`
876
877
878
879			`mas_0`
880			`0x00`
881
882
883
884
885			`mas_1`
886			`0x10`
887
888
889
890
891			`mas_2`
892			`0x20`
893
894
895
896
897			`mas_3`
898			`0x30`
899
900
901
902			`mas_4`
903			`0x40`
904
905
906
907
908			`mas_5`
909			`0x50`
910
911
912
913
914			`mas_6`
915			`0x60`
916
917
918
919
920			`mas_7`
921			`0x70`
922
923
924
925
926			`mas_8`
927			`0x80`
928
929
930
931
932
933
934
935
936
937
938
939
940
941			`mas_0`
942			`0x10`
943			`8`
944
945
946
947			`mas_1`
948			`0x10`
949			`8`
950
951
952
953			`mas_2`
954			`0x10`
955			`8`
956
957
958
959			`mas_3`
960			`0x10`
961			`8`
962
963
964
965			`mas_4`
966			`0x10`
967			`8`
968
969
970
971			`mas_5`
972			`0x10`
973			`8`
974
975
976
977			`mas_6`
978			`0x10`
979			`8`
980
981
982
983			`mas_7`
984			`0x10`
985			`8`
986
987
988
989			`mas_8`
990			`0x10`
991			`8`
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011