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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [icarus/] [default/] [wave.sav] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton 
[timestart] 0
2 
[size] 1920 1176
3 
[pos] 80 0
4 
*-11.000000 7220 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
5 
[treeopen] TB.
6 
[treeopen] TB.test.
7 
[treeopen] TB.test.dut.
8 
[treeopen] TB.test.dut.tim_0.
9 
@28
10 
TB.test.clk
11 
TB.test.reset
12 
TB.test.enable
13 
@22
14 
TB.test.reg_mb_addr[15:0]
15 
@28
16 
TB.test.reg_mb_cs
17 
TB.test.reg_mb_wr
18 
@22
19 
TB.test.reg_mb_wdata[7:0]
20 
@28
21 
TB.test.reg_mb_rd
22 
@22
23 
TB.test.reg_mb_rdata[15:0]
24 
TB.test.gpio_0_out[7:0]
25 
TB.test.gpio_0_oe[7:0]
26 
TB.test.gpio_0_lat[7:0]
27 
TB.test.gpio_0_in[7:0]
28 
TB.test.gpio_1_out[7:0]
29 
TB.test.gpio_1_oe[7:0]
30 
TB.test.gpio_1_lat[7:0]
31 
TB.test.gpio_1_in[7:0]
32 
TB.test.dut.gpio.gpio_0_out[7:0]
33 
TB.test.dut.gpio.next_gpio_0_out[7:0]
34 
TB.test.dut.tim_0.count_0[7:0]
35 
@28
36 
TB.test.dut.tim_0.state_0[2:0]
37 
@22
38 
TB.test.dut.tim_0.count_1[7:0]
39 
@28
40 
TB.test.dut.tim_0.state_1[2:0]
41 
@29
42 
TB.test.dut.tim_0.irq[1:0]
43 
[pattern_trace] 1
44 
[pattern_trace] 0

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