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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
micro_bus
def_tb
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      configuration
      default
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 
 
 
 

 

    addr_width16

 
 
       
 
 
 
              
              Params
              
                
                                   spirit:library="logic"
                                   spirit:name="micro_bus"
                                   spirit:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="micro_bus"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
   
      fs-lint
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 
 
 

 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`micro_bus`
40			`def_tb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56	133	jt_eaton	`configuration`
57			`default`
58
59
60	131	jt_eaton	`destination`
61			`top.tb`
62
63
64			`dest_dir`
65			`../verilog`
66
67
68			`top`
69
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87	133	jt_eaton	`addr_width16`
88	131	jt_eaton
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96			`Params`
97
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99			`spirit:library="logic"`
100			`spirit:name="micro_bus"`
101			`spirit:version="def_dut.params"/>`
102
103
104
105
106			`Bfm`
107
108			`spirit:library="logic"`
109			`spirit:name="micro_bus"`
110			`spirit:version="bfm.design"/>`
111
112
113
114
115			`icarus`
116
117
118			`spirit:library="Testbench"`
119			`spirit:name="toolflow"`
120			`spirit:version="icarus"/>`
121
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128
129			`commoncommon`
130			`Verilog`
131
132
133			`fs-common`
134
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139			`sim:Simulation:`
140			`Verilog`
141
142
143			`fs-sim`
144
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149			`lint:Lint:`
150			`Verilog`
151
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153			`fs-lint`
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174			`fs-common`
175
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178			`../verilog/tb.ext`
179			`verilogSourcefragment`
180
181
182
183
184
185
186			`fs-sim`
187
188
189
190
191			`../verilog/common/top.tb`
192			`verilogSourcemodule`
193
194
195
196
197
198
199
200
201
202			`fs-lint`
203
204
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207			`../verilog/common/top.tb`
208			`verilogSourcemodule`
209
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