URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_tb.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
micro_bus
def_tb
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      micro_bus_def_tb
    
  

 
 
 

 
 
 
 
 
 
 
 

 

    addr_width16

 
 
       
 
 
 
              
              Params
              
                
                                   spirit:library="logic"
                                   spirit:name="micro_bus"
                                   spirit:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="micro_bus"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/common/micro_bus_def_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
   
      fs-lint
 
 
      
        
        ../verilog/common/micro_bus_def_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 
 
 

 
 
 
 
 

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`micro_bus`
40			`def_tb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57	134	jt_eaton	`micro_bus_def_tb`
58	131	jt_eaton
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76	133	jt_eaton	`addr_width16`
77	131	jt_eaton
78
79
80
81
82
83
84
85			`Params`
86
87
88			`spirit:library="logic"`
89			`spirit:name="micro_bus"`
90			`spirit:version="def_dut.params"/>`
91
92
93
94
95			`Bfm`
96
97			`spirit:library="logic"`
98			`spirit:name="micro_bus"`
99			`spirit:version="bfm.design"/>`
100
101
102
103
104			`icarus`
105
106
107			`spirit:library="Testbench"`
108			`spirit:name="toolflow"`
109			`spirit:version="icarus"/>`
110
111
112
113
114
115
116
117
118			`commoncommon`
119			`Verilog`
120
121
122			`fs-common`
123
124
125
126
127
128			`sim:Simulation:`
129			`Verilog`
130
131
132			`fs-sim`
133
134
135
136
137
138			`lint:Lint:`
139			`Verilog`
140
141
142			`fs-lint`
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163			`fs-common`
164
165
166
167			`../verilog/tb.ext`
168			`verilogSourcefragment`
169
170
171
172
173
174
175			`fs-sim`
176
177
178
179
180	134	jt_eaton	`../verilog/common/micro_bus_def_tb`
181	131	jt_eaton	`verilogSourcemodule`
182
183
184
185
186
187
188
189
190
191			`fs-lint`
192
193
194
195
196	134	jt_eaton	`../verilog/common/micro_bus_def_tb`
197	131	jt_eaton	`verilogSourcemodule`
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_tb.xml] - Blame information for rev 134