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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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assign cde_serial_xmit_edge_enable =( load_tx_data && force_startbit) || ps2_clk_fall ;
assign cde_serial_xmit_load        =  load_tx_data && force_startbit;
assign cde_serial_rcvr_reset       =  reset ||(ps2_clk_s && ps2_data_s && !busy);
 
 
 
always@(posedge clk)
    begin
       if (reset)                                  tx_ack_error <= 1'b0 ;
       else
       if (tx_write)                               tx_ack_error <= 1'b0 ;
       else
       if ((bit_count == 4'b1010)&& ps2_clk_fall)  tx_ack_error <= ps2_data_s && sending ;
       else                                        tx_ack_error <= tx_ack_error ;
 
    end
 
 
 
`VARIANT`FSM
  #(.NUMBITS(11))
fsm
(
    .clk                        ( clk                         ),
    .reset                      ( reset                       ),
    .ps2_idle                   ( ps2_data_s &&   ps2_clk_s   ),
    .ps2_clk_fall               ( ps2_clk_fall                ),
    .bit_count                  ( bit_count                   ),
    .write                      ( tx_write                    ),
    .force_startbit             ( force_startbit              ),
    .usec_delay_done            ( usec_delay_done             ),
    .load_tx_data               ( load_tx_data                ),
    .ps2_clk_oe                 ( ps2_clk_pad_oe              ),
    .busy                       ( busy                        ),
    .shift_frame                ( shift_frame                 ),
    .enable_usec_delay          ( enable_usec_delay           )
);
 
 
 
always@(posedge clk )
if(reset)
         begin
         usec_prescale_count        <= FREQ-1;
         usec_tick                  <= 1'b0;
 end
   else
        begin
         if(enable_usec_delay )
   begin
            if(usec_prescale_count == 0)
              begin
               usec_prescale_count  <= FREQ-1;
               usec_tick            <= 1'b1;
      end
            else
      begin
               usec_prescale_count  <= usec_prescale_count - 1;
               usec_tick            <= 1'b0;
              end
            end
         else
            begin
            usec_prescale_count     <= FREQ-1;
            usec_tick               <= 1'b0;
            end
         end
 
 
 
always@(posedge clk )
if(reset)                                       force_startbit  <= 1'b0;
   else
        if(usec_delay_count <= DATA_SETUP_DELAY)        force_startbit  <= 1;
        else                                            force_startbit  <= 0;
 
 
 
 
 always@(posedge clk )
if(reset)
          begin
          usec_delay_count        <=  CLK_HOLD_DELAY + DATA_SETUP_DELAY;
          usec_delay_done         <=  0;
          end
   else
        if(enable_usec_delay )
  begin
          if(usec_delay_count == 7'b0000000)
            begin
            usec_delay_count      <=  usec_delay_count;
            usec_delay_done       <=  1;
    end
          else
  if(usec_tick)
    begin
            usec_delay_count      <=  usec_delay_count - 1;
            usec_delay_done       <=  0;
            end
          else
            begin
            usec_delay_count      <=  usec_delay_count;
            usec_delay_done       <=  usec_delay_done;
            end
          end
        else
          begin
          usec_delay_count        <=  CLK_HOLD_DELAY + DATA_SETUP_DELAY;
          usec_delay_done         <=  1'b0;
          end
 
 
 
 
    always@(posedge clk )
      if(reset)               bit_count  <= 4'b0000;
      else
      if(!busy)               bit_count  <= 4'b0000;
      else
      if(shift_frame)         bit_count  <= bit_count + 1;
      else                    bit_count  <= bit_count;
 
 
 
 
    always@(posedge clk )
      if(reset)               sending    <= 1'b0;
      else
      if(tx_write)            sending    <= 1'b1;
      else
      if(busy)                sending    <= sending;
      else                    sending    <= 1'b0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   always@(posedge clk)
     if(reset)
       begin
        rx_data          <=  8'h00;
        rx_read          <=  1'b0;
        rx_full          <=  1'b0;
        rx_parity_error  <=  1'b0;
        rx_parity_rcv    <=  1'b0;
rx_parity_cal    <=  1'b0;
        rx_frame_error   <=  1'b0;
end
     else
     if(rx_clear)
        begin
        rx_full          <=  1'b0;
        rx_read          <=  1'b0;
        rx_parity_error  <=  1'b0;
rx_parity_cal    <=  1'b0;
        rx_frame_error   <=  1'b0;
        end
     else
     if(x_last_cnt && !sending )
       begin
rx_data          <=   x_shift_buffer;
rx_read          <=  1'b1;
        rx_full          <=  1'b1;
        rx_parity_error  <=  x_parity_samp ^ x_parity_calc;
        rx_parity_rcv    <=  x_parity_samp;
rx_parity_cal    <=  x_parity_calc;
rx_frame_error   <=  x_frame_err;
        end
     else
        begin
        rx_full          <=  rx_full;
        rx_read          <=  1'b0;
        rx_parity_error  <=  rx_parity_error;
rx_frame_error   <=  rx_frame_error;
        rx_parity_rcv    <=  rx_parity_rcv;
        rx_parity_cal    <=  rx_parity_cal;
rx_data          <=  rx_data;
        end
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3			`assign cde_serial_xmit_edge_enable =( load_tx_data && force_startbit) \|\| ps2_clk_fall ;`
4			`assign cde_serial_xmit_load = load_tx_data && force_startbit;`
5			`assign cde_serial_rcvr_reset = reset \|\|(ps2_clk_s && ps2_data_s && !busy);`
6
7
8
9			`always@(posedge clk)`
10			`begin`
11			`if (reset) tx_ack_error <= 1'b0 ;`
12			`else`
13			`if (tx_write) tx_ack_error <= 1'b0 ;`
14			`else`
15			`if ((bit_count == 4'b1010)&& ps2_clk_fall) tx_ack_error <= ps2_data_s && sending ;`
16			`else tx_ack_error <= tx_ack_error ;`
17
18			`end`
19
20
21
22			`VARIANT`FSM
23			`#(.NUMBITS(11))`
24			`fsm`
25			`(`
26			`.clk ( clk ),`
27			`.reset ( reset ),`
28			`.ps2_idle ( ps2_data_s && ps2_clk_s ),`
29			`.ps2_clk_fall ( ps2_clk_fall ),`
30			`.bit_count ( bit_count ),`
31			`.write ( tx_write ),`
32			`.force_startbit ( force_startbit ),`
33			`.usec_delay_done ( usec_delay_done ),`
34			`.load_tx_data ( load_tx_data ),`
35			`.ps2_clk_oe ( ps2_clk_pad_oe ),`
36			`.busy ( busy ),`
37			`.shift_frame ( shift_frame ),`
38			`.enable_usec_delay ( enable_usec_delay )`
39			`);`
40
41
42
43			`always@(posedge clk )`
44			`if(reset)`
45			`begin`
46			`usec_prescale_count <= FREQ-1;`
47			`usec_tick <= 1'b0;`
48			`end`
49			`else`
50			`begin`
51			`if(enable_usec_delay )`
52			`begin`
53			`if(usec_prescale_count == 0)`
54			`begin`
55			`usec_prescale_count <= FREQ-1;`
56			`usec_tick <= 1'b1;`
57			`end`
58			`else`
59			`begin`
60			`usec_prescale_count <= usec_prescale_count - 1;`
61			`usec_tick <= 1'b0;`
62			`end`
63			`end`
64			`else`
65			`begin`
66			`usec_prescale_count <= FREQ-1;`
67			`usec_tick <= 1'b0;`
68			`end`
69			`end`
70
71
72
73			`always@(posedge clk )`
74			`if(reset) force_startbit <= 1'b0;`
75			`else`
76			`if(usec_delay_count <= DATA_SETUP_DELAY) force_startbit <= 1;`
77			`else force_startbit <= 0;`
78
79
80
81
82			`always@(posedge clk )`
83			`if(reset)`
84			`begin`
85			`usec_delay_count <= CLK_HOLD_DELAY + DATA_SETUP_DELAY;`
86			`usec_delay_done <= 0;`
87			`end`
88			`else`
89			`if(enable_usec_delay )`
90			`begin`
91			`if(usec_delay_count == 7'b0000000)`
92			`begin`
93			`usec_delay_count <= usec_delay_count;`
94			`usec_delay_done <= 1;`
95			`end`
96			`else`
97			`if(usec_tick)`
98			`begin`
99			`usec_delay_count <= usec_delay_count - 1;`
100			`usec_delay_done <= 0;`
101			`end`
102			`else`
103			`begin`
104			`usec_delay_count <= usec_delay_count;`
105			`usec_delay_done <= usec_delay_done;`
106			`end`
107			`end`
108			`else`
109			`begin`
110			`usec_delay_count <= CLK_HOLD_DELAY + DATA_SETUP_DELAY;`
111			`usec_delay_done <= 1'b0;`
112			`end`
113
114
115
116
117			`always@(posedge clk )`
118			`if(reset) bit_count <= 4'b0000;`
119			`else`
120			`if(!busy) bit_count <= 4'b0000;`
121			`else`
122			`if(shift_frame) bit_count <= bit_count + 1;`
123			`else bit_count <= bit_count;`
124
125
126
127
128			`always@(posedge clk )`
129			`if(reset) sending <= 1'b0;`
130			`else`
131			`if(tx_write) sending <= 1'b1;`
132			`else`
133			`if(busy) sending <= sending;`
134			`else sending <= 1'b0;`
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150			`always@(posedge clk)`
151			`if(reset)`
152			`begin`
153			`rx_data <= 8'h00;`
154			`rx_read <= 1'b0;`
155			`rx_full <= 1'b0;`
156			`rx_parity_error <= 1'b0;`
157			`rx_parity_rcv <= 1'b0;`
158			`rx_parity_cal <= 1'b0;`
159			`rx_frame_error <= 1'b0;`
160			`end`
161			`else`
162			`if(rx_clear)`
163			`begin`
164			`rx_full <= 1'b0;`
165			`rx_read <= 1'b0;`
166			`rx_parity_error <= 1'b0;`
167			`rx_parity_cal <= 1'b0;`
168			`rx_frame_error <= 1'b0;`
169			`end`
170			`else`
171			`if(x_last_cnt && !sending )`
172			`begin`
173			`rx_data <= x_shift_buffer;`
174			`rx_read <= 1'b1;`
175			`rx_full <= 1'b1;`
176			`rx_parity_error <= x_parity_samp ^ x_parity_calc;`
177			`rx_parity_rcv <= x_parity_samp;`
178			`rx_parity_cal <= x_parity_calc;`
179			`rx_frame_error <= x_frame_err;`
180			`end`
181			`else`
182			`begin`
183			`rx_full <= rx_full;`
184			`rx_read <= 1'b0;`
185			`rx_parity_error <= rx_parity_error;`
186			`rx_frame_error <= rx_frame_error;`
187			`rx_parity_rcv <= rx_parity_rcv;`
188			`rx_parity_cal <= rx_parity_cal;`
189			`rx_data <= rx_data;`
190			`end`
191
192
193
194
195

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [verilog/] [top.body] - Blame information for rev 131