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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [xml/] [ps2_interface_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
ps2_interface
def
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
          
      
  
 
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
          
      
  
 
 
 
 
 
 ps2
  
  
      
  
 
  
 
      
        clk_pad_oe
        ps2_clk_pad_oe
      
 
 
      
        clk_pad_in
        ps2_clk_pad_in
      
 
 
      
        data_pad_oe
        ps2_data_pad_oe
      
 
 
      
        data_pad_in
        ps2_data_pad_in
      
 
 
  
 
        
      
 
  
 
 
 
 
 
 
 
 
 
 

 
 
 
 

 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      ps2_interface_def
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      ps2_interface_def
    
  

 
 
 

 
 
 
 
 
 

 
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
  
 
              
                Hierarchical
                Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

 
busy
wire
out

 
tx_data
wire
in
70

 
tx_write
wire
in

 
rx_data
reg
out
70

 
rx_read
reg
out

 
rx_full
reg
out

 
rx_parity_error
reg
out

 
rx_parity_rcv
reg
out

 
rx_parity_cal
reg
out

 
rx_frame_error
reg
out

 
rx_clear
wire
in

 
tx_buffer_empty
wire
out

 
tx_ack_error
regx
out

 
 
 

 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/ps2_interface_def
        verilogSourcemodule
      
 
      
        fsm
        ../verilog/fsm
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
 
 
    
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/ps2_interface_def
        verilogSourcemodule
      
 
      
        fsm
        ../verilog/fsm
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
  
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [xml/] [ps2_interface_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`ps2_interface`
40			`def`
41	131	jt_eaton
42
43	135	jt_eaton
44	131	jt_eaton
45	135	jt_eaton	`slave_clk`
46
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59	131	jt_eaton
60	135	jt_eaton
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76
77
78	131	jt_eaton
79
80
81
82	135	jt_eaton	`ps2`
83
84
85
86
87	131	jt_eaton
88	135	jt_eaton
89	131	jt_eaton
90	135	jt_eaton
91			`clk_pad_oe`
92			`ps2_clk_pad_oe`
93
94	131	jt_eaton
95
96	135	jt_eaton
97			`clk_pad_in`
98			`ps2_clk_pad_in`
99
100	131	jt_eaton
101
102	135	jt_eaton
103			`data_pad_oe`
104			`ps2_data_pad_oe`
105
106	131	jt_eaton
107
108	135	jt_eaton
109			`data_pad_in`
110			`ps2_data_pad_in`
111
112	131	jt_eaton
113
114	135	jt_eaton
115
116
117
118	131	jt_eaton
119	135	jt_eaton
120	131	jt_eaton
121
122	135	jt_eaton
123	131	jt_eaton
124
125
126
127
128
129
130	135	jt_eaton
131	131	jt_eaton
132
133
134
135	135	jt_eaton
136	131	jt_eaton
137
138	135	jt_eaton
139			`gen_verilog_sim`
140			`104.0`
141			`none`
142			`:Simulation:`
143			`tools/verilog/gen_verilog`
144
145
146			`destination`
147			`ps2_interface_def`
148
149
150
151	131	jt_eaton
152	135	jt_eaton
153			`gen_verilog_syn`
154			`104.0`
155			`none`
156			`:Synthesis:`
157			`tools/verilog/gen_verilog`
158
159
160			`destination`
161			`ps2_interface_def`
162
163
164
165	131	jt_eaton
166
167
168	135	jt_eaton
169	131	jt_eaton
170
171
172
173
174
175	135	jt_eaton
176	131	jt_eaton
177
178
179	135	jt_eaton
180
181			`Hierarchical`
182
183
184
185
186
187
188
189
190			`Hierarchical`
191			`Hierarchical`
192
193
194
195
196			`verilog`
197
198
199			`ipxact:library="Testbench"`
200			`ipxact:name="toolflow"`
201			`ipxact:version="verilog"/>`
202
203
204
205
206
207
208
209
210			`sim:Simulation:`
211	131	jt_eaton
212	135	jt_eaton	`Verilog`
213
214
215			`fs-sim`
216
217
218	131	jt_eaton
219
220	135	jt_eaton
221			`syn:Synthesis:`
222	131	jt_eaton
223	135	jt_eaton	`Verilog`
224
225
226			`fs-syn`
227
228
229	131	jt_eaton
230
231	135	jt_eaton
232			`doc`
233
234
235			`ipxact:library="Testbench"`
236			`ipxact:name="toolflow"`
237			`ipxact:version="documentation"/>`
238
239			`:Documentation:`
240			`Verilog`
241
242	131	jt_eaton
243	135	jt_eaton
244	131	jt_eaton
245
246
247	135	jt_eaton
248	131	jt_eaton
249	135	jt_eaton	`busy`
250			`wire`
251			`out`
252
253	131	jt_eaton
254	135	jt_eaton	`tx_data`
255			`wire`
256			`in`
257			`70`
258
259	131	jt_eaton
260	135	jt_eaton	`tx_write`
261			`wire`
262			`in`
263
264	131	jt_eaton
265	135	jt_eaton	`rx_data`
266			`reg`
267			`out`
268			`70`
269
270	131	jt_eaton
271	135	jt_eaton	`rx_read`
272			`reg`
273			`out`
274
275	131	jt_eaton
276	135	jt_eaton	`rx_full`
277			`reg`
278			`out`
279
280	131	jt_eaton
281	135	jt_eaton	`rx_parity_error`
282			`reg`
283			`out`
284
285	131	jt_eaton
286	135	jt_eaton	`rx_parity_rcv`
287			`reg`
288			`out`
289
290	131	jt_eaton
291	135	jt_eaton	`rx_parity_cal`
292			`reg`
293			`out`
294
295	131	jt_eaton
296	135	jt_eaton	`rx_frame_error`
297			`reg`
298			`out`
299
300	131	jt_eaton
301	135	jt_eaton	`rx_clear`
302			`wire`
303			`in`
304
305	131	jt_eaton
306	135	jt_eaton	`tx_buffer_empty`
307			`wire`
308			`out`
309
310	131	jt_eaton
311	135	jt_eaton	`tx_ack_error`
312			`regx`
313			`out`
314
315	131	jt_eaton
316	135	jt_eaton
317	131	jt_eaton
318	135	jt_eaton
319	131	jt_eaton
320
321
322
323	135	jt_eaton
324	131	jt_eaton
325	135	jt_eaton
326			`fs-sim`
327	131	jt_eaton
328	135	jt_eaton
329
330			`../verilog/copyright`
331			`verilogSourceinclude`
332
333	134	jt_eaton
334	135	jt_eaton
335
336			`../verilog/sim/ps2_interface_def`
337			`verilogSourcemodule`
338
339	134	jt_eaton
340	135	jt_eaton
341			`fsm`
342			`../verilog/fsm`
343			`verilogSourcemodule`
344
345	134	jt_eaton
346	135	jt_eaton
347
348			`../verilog/top.body`
349			`verilogSourcefragment`
350
351	134	jt_eaton
352	135	jt_eaton
353
354			`../verilog/top.sim`
355			`verilogSourcefragment`
356
357	134	jt_eaton
358
359
360
361	135	jt_eaton
362			`dest_dir`
363			`../views/sim/`
364			`verilogSourcelibraryDir`
365
366	134	jt_eaton
367
368
369	135	jt_eaton
370	134	jt_eaton
371	135	jt_eaton
372			`fs-syn`
373	134	jt_eaton
374	135	jt_eaton
375
376			`../verilog/copyright`
377			`verilogSourceinclude`
378
379	134	jt_eaton
380	135	jt_eaton
381
382			`../verilog/syn/ps2_interface_def`
383			`verilogSourcemodule`
384
385	134	jt_eaton
386	135	jt_eaton
387			`fsm`
388			`../verilog/fsm`
389			`verilogSourcemodule`
390
391	134	jt_eaton
392	135	jt_eaton
393
394			`../verilog/top.body`
395			`verilogSourcefragment`
396
397	134	jt_eaton
398	135	jt_eaton
399			`dest_dir`
400			`../views/syn/`
401			`verilogSourcelibraryDir`
402
403	134	jt_eaton
404
405
406	135	jt_eaton
407	134	jt_eaton
408
409
410
411	135	jt_eaton
412	134	jt_eaton
413
414	135	jt_eaton