URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [xml/] [ps2_interface_def.xml] - Blame information for rev 131

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
ps2_interface
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 ps2
  
  
  
    
 
      
        clk_pad_oe
        ps2_clk_pad_oe
      
 
 
      
        clk_pad_in
        ps2_clk_pad_in
      
 
 
      
        data_pad_oe
        ps2_data_pad_oe
      
 
 
      
        data_pad_in
        ps2_data_pad_in
      
 
 
    
 
 
 
 
 
 
 
 

 
 
 
 

 
 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
      
        fsm
        ../verilog/fsm
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        fsm
        ../verilog/fsm
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="ps2_interface"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 
 
 
 
 

FREQ24
CLK_HOLD_DELAY100
DATA_SETUP_DELAY20
DEBOUNCE_DELAY4'b1111

 
 

 
busy
wire
out

 
tx_data
wire
in
70

 
tx_write
wire
in

 
rx_data
reg
out
70

 
rx_read
reg
out

 
rx_full
reg
out

 
rx_parity_error
reg
out

 
rx_parity_rcv
reg
out

 
rx_parity_cal
reg
out

 
rx_frame_error
reg
out

 
rx_clear
wire
in

 
tx_buffer_empty
wire
out

 
tx_ack_error
regx
out

 
 
 

 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [xml/] [ps2_interface_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`ps2_interface`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72
73			`ps2`
74
75
76
77
78
79
80			`clk_pad_oe`
81			`ps2_clk_pad_oe`
82
83
84
85
86			`clk_pad_in`
87			`ps2_clk_pad_in`
88
89
90
91
92			`data_pad_oe`
93			`ps2_data_pad_oe`
94
95
96
97
98			`data_pad_in`
99			`ps2_data_pad_in`
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126			`gen_verilog_sim`
127			`104.0`
128			`none`
129			`:Simulation:`
130			`./tools/verilog/gen_verilog`
131
132
133			`destination`
134			`top.out.sim`
135
136
137			`dest_dir`
138			`../verilog`
139
140
141
142
143
144			`gen_verilog_syn`
145			`104.0`
146			`none`
147			`:Synthesis:`
148			`./tools/verilog/gen_verilog`
149
150
151			`destination`
152			`top.out.syn`
153
154
155			`dest_dir`
156			`../verilog`
157
158
159
160
161
162
163
164
165
166
167
168
169
170			`fs-sim`
171
172
173
174			`../verilog/copyright.v`
175			`verilogSourceinclude`
176
177
178
179
180			`../verilog/sim/top.out.sim`
181			`verilogSourcemodule`
182
183
184
185			`fsm`
186			`../verilog/fsm`
187			`verilogSourcemodule`
188
189
190
191
192			`../verilog/top.body`
193			`verilogSourcefragment`
194
195
196
197
198			`../verilog/top.sim`
199			`verilogSourcefragment`
200
201
202
203
204
205
206
207			`fs-syn`
208
209
210
211			`../verilog/copyright.v`
212			`verilogSourceinclude`
213
214
215
216
217			`../verilog/syn/top.out.syn`
218			`verilogSourcemodule`
219
220
221
222			`fsm`
223			`../verilog/fsm`
224			`verilogSourcemodule`
225
226
227
228
229			`../verilog/top.body`
230			`verilogSourcefragment`
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247			`Hierarchical`
248
249
250			`spirit:library="logic"`
251			`spirit:name="ps2_interface"`
252			`spirit:version="def.design"/>`
253
254
255
256
257			`verilog`
258
259
260			`spirit:library="Testbench"`
261			`spirit:name="toolflow"`
262			`spirit:version="verilog"/>`
263
264
265
266
267
268
269
270
271			`sim:Simulation:`
272
273			`Verilog`
274
275
276			`fs-sim`
277
278
279
280
281
282			`syn:Synthesis:`
283
284			`Verilog`
285
286
287			`fs-syn`
288
289
290
291
292
293			`doc`
294
295
296			`spirit:library="Testbench"`
297			`spirit:name="toolflow"`
298			`spirit:version="documentation"/>`
299
300			`:Documentation:`
301			`Verilog`
302
303
304
305
306
307
308
309
310
311
312
313
314			`FREQ24`
315			`CLK_HOLD_DELAY100`
316			`DATA_SETUP_DELAY20`
317			`DEBOUNCE_DELAY4'b1111`
318
319
320
321
322
323			`busy`
324			`wire`
325			`out`
326
327
328			`tx_data`
329			`wire`
330			`in`
331			`70`
332
333
334			`tx_write`
335			`wire`
336			`in`
337
338
339			`rx_data`
340			`reg`
341			`out`
342			`70`
343
344
345			`rx_read`
346			`reg`
347			`out`
348
349
350			`rx_full`
351			`reg`
352			`out`
353
354
355			`rx_parity_error`
356			`reg`
357			`out`
358
359
360			`rx_parity_rcv`
361			`reg`
362			`out`
363
364
365			`rx_parity_cal`
366			`reg`
367			`out`
368
369
370			`rx_frame_error`
371			`reg`
372			`out`
373
374
375			`rx_clear`
376			`wire`
377			`in`
378
379
380			`tx_buffer_empty`
381			`wire`
382			`out`
383
384
385			`tx_ack_error`
386			`regx`
387			`out`
388
389
390
391
392
393
394
395
396
397
398
399