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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [sim/] [testbenches/] [xml/] [ps2_interface_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
ps2_interface
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      ps2_interface_def_tb
    
  

 
 
 
 

 
 
 
 

 
 

    PS2_MODEL_CLKCNT8'h7f

 
 
       
 
              
              Params
              
              
                                   ipxact:library="logic"
                                   ipxact:name="ps2_interface"
                                   ipxact:version="def_dut.params"/>
             
              
 
 
 
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="ps2_interface"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
 
 
              
              common:*common:*
              Verilog
              
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
      
 
 
 
 
 
 
 
 

 
 
 
  
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/ps2_interface_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/ps2_interface_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`ps2_interface`
40			`def_tb`
41	131	jt_eaton
42
43
44
45
46
47	135	jt_eaton
48	131	jt_eaton
49
50
51	135	jt_eaton
52			`gen_verilog`
53			`104.0`
54			`none`
55			`:common:`
56			`tools/verilog/gen_verilog`
57
58
59			`destination`
60			`ps2_interface_def_tb`
61
62
63
64	131	jt_eaton
65
66
67
68	135	jt_eaton
69	131	jt_eaton
70
71
72
73	135	jt_eaton
74	131	jt_eaton
75
76	135	jt_eaton
77			`PS2_MODEL_CLKCNT8'h7f`
78
79	131	jt_eaton
80
81	135	jt_eaton
82	131	jt_eaton
83	135	jt_eaton
84			`Params`
85
86
87			`ipxact:library="logic"`
88			`ipxact:name="ps2_interface"`
89			`ipxact:version="def_dut.params"/>`
90
91
92	131	jt_eaton
93
94
95
96	135	jt_eaton
97			`Bfm`
98
99			`ipxact:library="logic"`
100			`ipxact:name="ps2_interface"`
101			`ipxact:version="bfm.design"/>`
102
103	131	jt_eaton
104
105
106	135	jt_eaton
107			`icarus`
108
109
110			`ipxact:library="Testbench"`
111			`ipxact:name="toolflow"`
112			`ipxact:version="icarus"/>`
113
114
115	131	jt_eaton
116
117
118
119
120
121	135	jt_eaton
122			`common:common:`
123			`Verilog`
124
125
126	131	jt_eaton
127
128	135	jt_eaton
129			`sim:Simulation:`
130			`Verilog`
131
132
133			`fs-sim`
134
135
136	131	jt_eaton
137
138	135	jt_eaton
139			`lint:Lint:`
140			`Verilog`
141
142
143			`fs-lint`
144
145
146	131	jt_eaton
147
148
149	135	jt_eaton
150	131	jt_eaton
151
152
153
154
155
156
157
158	135	jt_eaton
159	131	jt_eaton
160
161
162	135	jt_eaton
163	131	jt_eaton
164
165
166	135	jt_eaton
167			`fs-sim`
168	131	jt_eaton
169	135	jt_eaton
170
171			`../verilog/common/ps2_interface_def_tb`
172			`verilogSourcemodule`
173
174	131	jt_eaton
175
176
177	135	jt_eaton
178	131	jt_eaton
179
180
181	135	jt_eaton
182			`fs-lint`
183	131	jt_eaton
184	135	jt_eaton
185
186			`../verilog/common/ps2_interface_def_tb`
187			`verilogSourcemodule`
188
189	131	jt_eaton
190
191
192	135	jt_eaton
193	131	jt_eaton
194
195
196
197
198	135	jt_eaton
199	131	jt_eaton
200
201	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [sim/] [testbenches/] [xml/] [ps2_interface_def_tb.xml] - Blame information for rev 135