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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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always@(posedge clk)
if(reset)                                              rxd_pad_sig <= 1'b1;
else                                                   rxd_pad_sig <= pad_in;
 
 
always@(posedge clk)
if(reset)                                              start_detect <= 1'b0;
else
if(start_detect)
  begin
    if(stop_cnt  && edge_enable )                      start_detect <= !(rxd_pad_sig ^ START_VALUE);
    else
    if(last_cnt)                                       start_detect <= 1'b0;
    else                                               start_detect <= 1'b1;
  end
else
if(!(rxd_pad_sig ^ START_VALUE) )                      start_detect <= 1'b1;
else                                                   start_detect <= start_detect;
 
 
always@(posedge clk)
  if(reset)
    begin
    frame_rdy <= 1'b0;
    rdy_del   <= 2'b00;
    end
  else
    begin
    frame_rdy <=  rdy_del[1] ;
    rdy_del   <=  {rdy_del[0],last_cnt};
    end
 
 always@(posedge clk)
   if (reset)                                       frame_avail <= 1'b0;
   else
   if(frame_rdy)                                    frame_avail <= 1'b1;
   else
   if(rcv_stb)                                      frame_avail <= 1'b0;
   else                                             frame_avail <= frame_avail;
 
 
 
always@(posedge clk)
  if(reset)
     begin
          shift_buffer   <=  8'h00;
          parity_calc    <=  1'b0;
          parity_samp    <=  1'b0;
          frame_parity_error   <=  1'b0;
          frame_error    <=  1'b0;
     end
  else
  if(last_cnt )
      begin
          shift_buffer   <=  next_shift_buffer;
          parity_calc    <=  next_parity_calc;
          parity_samp    <=  next_parity_samp;
          frame_parity_error   <=  (next_parity_samp ^ next_parity_calc) && parity_enable;
          frame_error    <=  next_frame_error;
      end
  else
     begin
          shift_buffer   <=  shift_buffer;
          parity_calc    <=  parity_calc;
          parity_samp    <=  parity_samp;
          frame_parity_error   <=  frame_parity_error;
          frame_error    <=  frame_error;
      end
 
 
assign    divider_reset = reset || (!start_detect);
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`always@(posedge clk)`
3			`if(reset) rxd_pad_sig <= 1'b1;`
4			`else rxd_pad_sig <= pad_in;`
5
6
7			`always@(posedge clk)`
8			`if(reset) start_detect <= 1'b0;`
9			`else`
10			`if(start_detect)`
11			`begin`
12			`if(stop_cnt && edge_enable ) start_detect <= !(rxd_pad_sig ^ START_VALUE);`
13			`else`
14			`if(last_cnt) start_detect <= 1'b0;`
15			`else start_detect <= 1'b1;`
16			`end`
17			`else`
18			`if(!(rxd_pad_sig ^ START_VALUE) ) start_detect <= 1'b1;`
19			`else start_detect <= start_detect;`
20
21
22			`always@(posedge clk)`
23			`if(reset)`
24			`begin`
25			`frame_rdy <= 1'b0;`
26			`rdy_del <= 2'b00;`
27			`end`
28			`else`
29			`begin`
30			`frame_rdy <= rdy_del[1] ;`
31			`rdy_del <= {rdy_del[0],last_cnt};`
32			`end`
33
34			`always@(posedge clk)`
35			`if (reset) frame_avail <= 1'b0;`
36			`else`
37			`if(frame_rdy) frame_avail <= 1'b1;`
38			`else`
39			`if(rcv_stb) frame_avail <= 1'b0;`
40			`else frame_avail <= frame_avail;`
41
42
43
44			`always@(posedge clk)`
45			`if(reset)`
46			`begin`
47			`shift_buffer <= 8'h00;`
48			`parity_calc <= 1'b0;`
49			`parity_samp <= 1'b0;`
50			`frame_parity_error <= 1'b0;`
51			`frame_error <= 1'b0;`
52			`end`
53			`else`
54			`if(last_cnt )`
55			`begin`
56			`shift_buffer <= next_shift_buffer;`
57			`parity_calc <= next_parity_calc;`
58			`parity_samp <= next_parity_samp;`
59			`frame_parity_error <= (next_parity_samp ^ next_parity_calc) && parity_enable;`
60			`frame_error <= next_frame_error;`
61			`end`
62			`else`
63			`begin`
64			`shift_buffer <= shift_buffer;`
65			`parity_calc <= parity_calc;`
66			`parity_samp <= parity_samp;`
67			`frame_parity_error <= frame_parity_error;`
68			`frame_error <= frame_error;`
69			`end`
70
71
72			`assign divider_reset = reset \|\| (!start_detect);`
73
74
75
76
77
78
79
80

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [verilog/] [top.body] - Blame information for rev 131