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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
serial_rcvr
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/no_fifo
        verilogSourcefragment
      
 
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
  
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="serial_rcvr"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

WIDTH8
SIZE4
SAMPLE4'b0111
START_VALUE1'b0
STOP_VALUE1'b1

 

 
 
edge_enable
wire
in

 
parity_enable
wire
in

 
parity_type
wire
in

 
parity_force
wire
in

 
 
 
 
pad_in
wire
in

 
rcv_stb
wire
in

 
data_out
wire
out
WIDTH-10

 
parity_error
wire
out

 
stop_error
wire
out

 
data_avail
wire
out

 

 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72
73
74
75
76
77
78
79	133	jt_eaton
80			`elab_verilog`
81			`102.1`
82			`none`
83			`:Simulation:`
84			`./tools/verilog/elab_verilog`
85
86
87			`dest_dir`
88			`io_ports`
89
90
91
92	131	jt_eaton
93
94
95	133	jt_eaton
96	131	jt_eaton
97			`gen_verilog`
98			`104.0`
99			`none`
100			`common`
101			`./tools/verilog/gen_verilog`
102
103
104			`destination`
105			`top`
106
107
108			`dest_dir`
109			`../verilog`
110
111
112
113
114
115
116
117
118
119
120
121			`fs-common`
122
123
124
125			`../verilog/top.body`
126			`verilogSourcefragment`
127
128
129
130
131			`../verilog/no_fifo`
132			`verilogSourcefragment`
133
134
135
136
137
138
139
140			`fs-sim`
141
142
143
144			`../verilog/copyright.v`
145			`verilogSourceinclude`
146
147
148
149
150			`../verilog/common/top`
151			`verilogSourcemodule`
152
153
154
155
156
157
158
159
160			`fs-syn`
161
162
163
164			`../verilog/copyright.v`
165			`verilogSourceinclude`
166
167
168
169
170			`../verilog/common/top`
171			`verilogSourcemodule`
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188			`Hierarchical`
189
190
191			`spirit:library="logic"`
192			`spirit:name="serial_rcvr"`
193			`spirit:version="def.design"/>`
194
195
196
197			`verilog`
198
199
200			`spirit:library="Testbench"`
201			`spirit:name="toolflow"`
202			`spirit:version="verilog"/>`
203
204
205
206
207
208
209
210
211			`commoncommon`
212			`Verilog`
213
214
215			`fs-common`
216
217
218
219
220
221
222			`sim:Simulation:`
223			`Verilog`
224
225
226			`fs-sim`
227
228
229
230
231
232
233			`syn:Synthesis:`
234			`Verilog`
235
236
237			`fs-syn`
238
239
240
241
242
243
244			`doc`
245
246
247			`spirit:library="Testbench"`
248			`spirit:name="toolflow"`
249			`spirit:version="documentation"/>`
250
251			`:Documentation:`
252			`Verilog`
253
254
255
256
257
258
259
260
261
262
263			`WIDTH8`
264			`SIZE4`
265			`SAMPLE4'b0111`
266			`START_VALUE1'b0`
267			`STOP_VALUE1'b1`
268
269
270
271
272
273			`edge_enable`
274			`wire`
275			`in`
276
277
278			`parity_enable`
279			`wire`
280			`in`
281
282
283			`parity_type`
284			`wire`
285			`in`
286
287
288			`parity_force`
289			`wire`
290			`in`
291
292
293
294
295
296			`pad_in`
297			`wire`
298			`in`
299
300
301			`rcv_stb`
302			`wire`
303			`in`
304
305
306			`data_out`
307			`wire`
308			`out`
309			`WIDTH-10`
310
311
312			`parity_error`
313			`wire`
314			`out`
315
316
317			`stop_error`
318			`wire`
319			`out`
320
321
322			`data_avail`
323			`wire`
324			`out`
325
326
327
328
329
330
331
332
333
334
335
336
337