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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
serial_rcvr
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      serial_rcvr_def
    
  

 
 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/no_fifo
        verilogSourcefragment
      
 
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/serial_rcvr_def
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/serial_rcvr_def
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
  
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="serial_rcvr"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

WIDTH8
SIZE4
SAMPLE4'b0111
START_VALUE1'b0
STOP_VALUE1'b1

 

 
 
edge_enable
wire
in

 
parity_enable
wire
in

 
parity_type
wire
in

 
parity_force
wire
in

 
 
 
 
pad_in
wire
in

 
rcv_stb
wire
in

 
data_out
wire
out
WIDTH-10

 
parity_error
wire
out

 
stop_error
wire
out

 
data_avail
wire
out

 

 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72
73
74
75
76
77	133	jt_eaton
78	131	jt_eaton	`gen_verilog`
79			`104.0`
80			`none`
81			`common`
82			`./tools/verilog/gen_verilog`
83
84
85			`destination`
86	134	jt_eaton	`serial_rcvr_def`
87	131	jt_eaton
88
89
90
91
92
93
94
95
96
97
98			`fs-common`
99
100
101
102			`../verilog/top.body`
103			`verilogSourcefragment`
104
105
106
107
108			`../verilog/no_fifo`
109			`verilogSourcefragment`
110
111
112
113
114
115
116
117			`fs-sim`
118
119
120
121	134	jt_eaton	`../verilog/copyright`
122	131	jt_eaton	`verilogSourceinclude`
123
124
125
126
127	134	jt_eaton	`../verilog/common/serial_rcvr_def`
128	131	jt_eaton	`verilogSourcemodule`
129
130
131
132	134	jt_eaton
133			`dest_dir`
134			`../views/sim/`
135			`verilogSourcelibraryDir`
136
137
138
139
140
141	131	jt_eaton
142
143
144
145
146			`fs-syn`
147
148
149
150	134	jt_eaton	`../verilog/copyright`
151	131	jt_eaton	`verilogSourceinclude`
152
153
154
155
156	134	jt_eaton	`../verilog/common/serial_rcvr_def`
157	131	jt_eaton	`verilogSourcemodule`
158
159
160	134	jt_eaton
161			`dest_dir`
162			`../views/syn/`
163			`verilogSourcelibraryDir`
164
165	131	jt_eaton
166
167	134	jt_eaton
168	131	jt_eaton
169
170
171
172
173
174
175
176
177
178
179
180			`Hierarchical`
181
182
183			`spirit:library="logic"`
184			`spirit:name="serial_rcvr"`
185			`spirit:version="def.design"/>`
186
187
188
189			`verilog`
190
191
192			`spirit:library="Testbench"`
193			`spirit:name="toolflow"`
194			`spirit:version="verilog"/>`
195
196
197
198
199
200
201
202
203			`commoncommon`
204			`Verilog`
205
206
207			`fs-common`
208
209
210
211
212
213
214			`sim:Simulation:`
215			`Verilog`
216
217
218			`fs-sim`
219
220
221
222
223
224
225			`syn:Synthesis:`
226			`Verilog`
227
228
229			`fs-syn`
230
231
232
233
234
235	134	jt_eaton
236
237
238	131	jt_eaton
239			`doc`
240
241
242			`spirit:library="Testbench"`
243			`spirit:name="toolflow"`
244			`spirit:version="documentation"/>`
245
246			`:Documentation:`
247			`Verilog`
248
249
250
251
252
253
254
255
256
257
258			`WIDTH8`
259			`SIZE4`
260			`SAMPLE4'b0111`
261			`START_VALUE1'b0`
262			`STOP_VALUE1'b1`
263
264
265
266
267
268			`edge_enable`
269			`wire`
270			`in`
271
272
273			`parity_enable`
274			`wire`
275			`in`
276
277
278			`parity_type`
279			`wire`
280			`in`
281
282
283			`parity_force`
284			`wire`
285			`in`
286
287
288
289
290
291			`pad_in`
292			`wire`
293			`in`
294
295
296			`rcv_stb`
297			`wire`
298			`in`
299
300
301			`data_out`
302			`wire`
303			`out`
304			`WIDTH-10`
305
306
307			`parity_error`
308			`wire`
309			`out`
310
311
312			`stop_error`
313			`wire`
314			`out`
315
316
317			`data_avail`
318			`wire`
319			`out`
320
321
322
323
324
325
326
327
328
329
330
331
332