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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_fifo.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
serial_rcvr
fifo.design
 
 
 

 
 
baud_enable
wire
 

 
stop_cnt
wire
 

 
last_cnt
wire
 

 
next_shift_buffer
wire

WIDTH-10

 
next_parity_calc
wire
 

 
next_parity_samp
wire
 

 
next_frame_error
wire
 

 
parity_calc
reg
 

 
parity_samp
reg
 

 
frame_rdy
reg
 

 
start_detect
reg
 

 
rxd_pad_sig
reg
 

 
rdy_del
reg

10

 
shift_buffer
reg

WIDTH-10

 
frame_parity_error
reg
 

 
frame_error
reg
 

 
frame_avail
reg
 

 
 
divider_reset
wire
 

 
 
 
 
 
fifo_full
wire
 

 
 
fifo_empty
wire
 

 
 
fifo_over_run
wire
 

 
fifo_under_run
wire
 

 
fifo_din
wire

WIDTH+10

 
fifo_dout
wire

WIDTH+10

 
 
 
 

 

 
 
    
      clk
      
      
      
      
    
 
 
    
      reset
      
      
      
    
 
 
    
      divider_reset
      
    
 
    
      edge_enable
      
      
    
 
    
 
      
    
 
    
      baud_enable
      
      
    
 
 
    
      parity_enable
      
      
    
 
 
    
      parity_type
      
      
    
 
 
    
      parity_force
      
      
    
 
 
    
      stop_cnt
      
      
    
 
 
    
      last_cnt
      
      
    
 
 
 
    
      pad_in
      
      
    
 
    
      next_shift_buffer
      
      
    
 
    
      next_parity_calc
      
      
    
 
    
      next_parity_samp
      
      
    
 
    
      next_frame_error
      
    
 
 
    
      last_cnt
      
      
    
 
    
      fifo_din
      
    
 
 
    
      rcv_stb
      
      
    
 
 
    
      fifo_dout
      
    
 
    
      fifo_full
      
      
    
 
    
      fifo_empty
      
      
    
 
    
      fifo_over_run
      
      
    
 
    
      fifo_under_run
      
      
    
 
 
 

 

 
 
 

divider 
 
 4
 8
 0


 

serial_rcvr 
 
 WIDTH
 SIZE
 1
 STOP_VALUE
 

 
 

fifo 
 
 WIDTH+2
 RX_FIFO_SIZE
 RX_FIFO_WORDS
 

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_fifo.design.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`fifo.design`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47	135	jt_eaton	`baud_enable`
48			`wire`
49	131	jt_eaton
50
51
52	135	jt_eaton	`stop_cnt`
53			`wire`
54	131	jt_eaton
55
56
57	135	jt_eaton	`last_cnt`
58			`wire`
59	131	jt_eaton
60
61
62	135	jt_eaton	`next_shift_buffer`
63			`wire`
64
65			`WIDTH-10`
66	131	jt_eaton
67
68	135	jt_eaton	`next_parity_calc`
69			`wire`
70	131	jt_eaton
71
72
73	135	jt_eaton	`next_parity_samp`
74			`wire`
75	131	jt_eaton
76
77
78	135	jt_eaton	`next_frame_error`
79			`wire`
80	131	jt_eaton
81
82
83	135	jt_eaton	`parity_calc`
84			`reg`
85	131	jt_eaton
86
87
88	135	jt_eaton	`parity_samp`
89			`reg`
90	131	jt_eaton
91
92
93	135	jt_eaton	`frame_rdy`
94			`reg`
95	131	jt_eaton
96
97
98	135	jt_eaton	`start_detect`
99			`reg`
100	131	jt_eaton
101
102
103	135	jt_eaton	`rxd_pad_sig`
104			`reg`
105	131	jt_eaton
106
107
108	135	jt_eaton	`rdy_del`
109			`reg`
110
111			`10`
112	131	jt_eaton
113
114	135	jt_eaton	`shift_buffer`
115			`reg`
116
117			`WIDTH-10`
118	131	jt_eaton
119
120	135	jt_eaton	`frame_parity_error`
121			`reg`
122	131	jt_eaton
123
124
125	135	jt_eaton	`frame_error`
126			`reg`
127	131	jt_eaton
128
129
130	135	jt_eaton	`frame_avail`
131			`reg`
132	131	jt_eaton
133
134
135
136	135	jt_eaton	`divider_reset`
137			`wire`
138	131	jt_eaton
139
140
141
142
143
144
145	135	jt_eaton	`fifo_full`
146			`wire`
147	131	jt_eaton
148
149
150
151	135	jt_eaton	`fifo_empty`
152			`wire`
153	131	jt_eaton
154
155
156
157	135	jt_eaton	`fifo_over_run`
158			`wire`
159	131	jt_eaton
160
161
162	135	jt_eaton	`fifo_under_run`
163			`wire`
164	131	jt_eaton
165
166
167	135	jt_eaton	`fifo_din`
168			`wire`
169
170			`WIDTH+10`
171	131	jt_eaton
172
173	135	jt_eaton	`fifo_dout`
174			`wire`
175
176			`WIDTH+10`
177	131	jt_eaton
178
179
180
181
182	135	jt_eaton
183	131	jt_eaton
184	135	jt_eaton
185	131	jt_eaton
186
187	135	jt_eaton
188			`clk`
189
190
191
192
193
194	131	jt_eaton
195
196	135	jt_eaton
197			`reset`
198
199
200
201
202	131	jt_eaton
203
204	135	jt_eaton
205			`divider_reset`
206
207
208	131	jt_eaton
209	135	jt_eaton
210			`edge_enable`
211
212
213
214	131	jt_eaton
215	135	jt_eaton
216	131	jt_eaton
217	135	jt_eaton
218
219	131	jt_eaton
220	135	jt_eaton
221			`baud_enable`
222
223
224
225	131	jt_eaton
226
227	135	jt_eaton
228			`parity_enable`
229
230
231
232	131	jt_eaton
233
234	135	jt_eaton
235			`parity_type`
236
237
238
239	131	jt_eaton
240
241	135	jt_eaton
242			`parity_force`
243
244
245
246	131	jt_eaton
247
248	135	jt_eaton
249			`stop_cnt`
250
251
252
253	131	jt_eaton
254
255	135	jt_eaton
256			`last_cnt`
257
258
259
260	131	jt_eaton
261
262
263	135	jt_eaton
264			`pad_in`
265
266
267
268	131	jt_eaton
269	135	jt_eaton
270			`next_shift_buffer`
271
272
273
274	131	jt_eaton
275	135	jt_eaton
276			`next_parity_calc`
277
278
279
280	131	jt_eaton
281	135	jt_eaton
282			`next_parity_samp`
283
284
285
286	131	jt_eaton
287	135	jt_eaton
288			`next_frame_error`
289
290
291	131	jt_eaton
292
293	135	jt_eaton
294			`last_cnt`
295
296
297
298	131	jt_eaton
299	135	jt_eaton
300			`fifo_din`
301
302
303	131	jt_eaton
304
305	135	jt_eaton
306			`rcv_stb`
307
308
309
310	131	jt_eaton
311
312	135	jt_eaton
313			`fifo_dout`
314
315
316	131	jt_eaton
317	135	jt_eaton
318			`fifo_full`
319
320
321
322	131	jt_eaton
323	135	jt_eaton
324			`fifo_empty`
325
326
327
328	131	jt_eaton
329	135	jt_eaton
330			`fifo_over_run`
331
332
333
334	131	jt_eaton
335	135	jt_eaton
336			`fifo_under_run`
337
338
339
340	131	jt_eaton
341
342
343	135	jt_eaton
344	131	jt_eaton
345	135	jt_eaton
346	131	jt_eaton
347
348
349	135	jt_eaton
350			`divider`
351
352			`4`
353			`8`
354			`0`
355
356
357	131	jt_eaton
358	135	jt_eaton
359			`serial_rcvr`
360
361			`WIDTH`
362			`SIZE`
363			`1`
364			`STOP_VALUE`
365
366
367	131	jt_eaton
368
369	135	jt_eaton
370			`fifo`
371
372			`WIDTH+2`
373			`RX_FIFO_SIZE`
374			`RX_FIFO_WORDS`
375
376
377	131	jt_eaton
378
379
380	135	jt_eaton
381	131	jt_eaton
382
383
384
385
386
387
388
389
390
391
392
393
394	135	jt_eaton