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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_fifo.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
serial_rcvr
fifo  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.fifo
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 

 
 
 
 
  
 
    
      fs-common
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
      
        
        ../verilog/fifo
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.fifo
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-syn
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.fifo
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="serial_rcvr"
                                   spirit:version="fifo.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

WIDTH8
SIZE4
SAMPLE4'b0111
START_VALUE1'b0
STOP_VALUE1'b1
RX_FIFO_SIZE4
RX_FIFO_WORDS16

 

 
 
edge_enable
wire
in

 
parity_enable
wire
in

 
parity_type
wire
in

 
parity_force
wire
in

 
 
 
 
pad_in
wire
in

 
rcv_stb
wire
in

 
data_out
wire
out
WIDTH-10

 
parity_error
wire
out

 
stop_error
wire
out

 
data_avail
wire
out

 

 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_fifo.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`fifo default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73
74
75
76
77
78
79	133	jt_eaton
80			`elab_verilog`
81			`102.1`
82			`none`
83			`:Simulation:`
84			`./tools/verilog/elab_verilog`
85
86
87			`dest_dir`
88			`io_ports`
89
90
91
92	131	jt_eaton
93
94	133	jt_eaton
95
96	131	jt_eaton
97			`gen_verilog`
98			`104.0`
99			`none`
100			`common`
101			`./tools/verilog/gen_verilog`
102
103
104			`destination`
105			`top.fifo`
106
107
108			`dest_dir`
109			`../verilog`
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127			`fs-common`
128
129
130
131
132			`../verilog/top.body`
133			`verilogSourcefragment`
134
135
136
137
138
139			`../verilog/fifo`
140			`verilogSourcefragment`
141
142
143
144
145
146
147
148
149
150			`fs-sim`
151
152
153
154			`../verilog/copyright.v`
155			`verilogSourceinclude`
156
157
158
159
160			`../verilog/common/top.fifo`
161			`verilogSourcemodule`
162
163
164
165
166
167
168
169
170			`fs-syn`
171
172
173
174
175			`../verilog/copyright.v`
176			`verilogSourceinclude`
177
178
179
180
181			`../verilog/common/top.fifo`
182			`verilogSourcemodule`
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200			`Hierarchical`
201
202
203			`spirit:library="logic"`
204			`spirit:name="serial_rcvr"`
205			`spirit:version="fifo.design"/>`
206
207
208
209
210			`verilog`
211
212
213			`spirit:library="Testbench"`
214			`spirit:name="toolflow"`
215			`spirit:version="verilog"/>`
216
217
218
219
220
221
222
223
224			`commoncommon`
225			`Verilog`
226
227
228			`fs-common`
229
230
231
232
233
234
235			`sim:Simulation:`
236			`Verilog`
237
238
239			`fs-sim`
240
241
242
243
244
245			`syn:Synthesis:`
246			`Verilog`
247
248
249			`fs-syn`
250
251
252
253
254
255			`doc`
256
257
258			`spirit:library="Testbench"`
259			`spirit:name="toolflow"`
260			`spirit:version="documentation"/>`
261
262			`:Documentation:`
263			`Verilog`
264
265
266
267
268
269
270
271
272
273
274			`WIDTH8`
275			`SIZE4`
276			`SAMPLE4'b0111`
277			`START_VALUE1'b0`
278			`STOP_VALUE1'b1`
279			`RX_FIFO_SIZE4`
280			`RX_FIFO_WORDS16`
281
282
283
284
285
286			`edge_enable`
287			`wire`
288			`in`
289
290
291			`parity_enable`
292			`wire`
293			`in`
294
295
296			`parity_type`
297			`wire`
298			`in`
299
300
301			`parity_force`
302			`wire`
303			`in`
304
305
306
307
308
309			`pad_in`
310			`wire`
311			`in`
312
313
314			`rcv_stb`
315			`wire`
316			`in`
317
318
319			`data_out`
320			`wire`
321			`out`
322			`WIDTH-10`
323
324
325			`parity_error`
326			`wire`
327			`out`
328
329
330			`stop_error`
331			`wire`
332			`out`
333
334
335			`data_avail`
336			`wire`
337			`out`
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353