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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_fifo.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
serial_rcvr
fifo  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      serial_rcvr_fifo
    
  

 
 
 
 
 
 

 
 
 
 
  
 
    
      fs-common
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
      
        
        ../verilog/fifo
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/serial_rcvr_fifo
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
    
      fs-syn
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/serial_rcvr_fifo
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="serial_rcvr"
                                   spirit:version="fifo.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
edge_enable
wire
in

 
parity_enable
wire
in

 
parity_type
wire
in

 
parity_force
wire
in

 
 
 
 
pad_in
wire
in

 
rcv_stb
wire
in

 
data_out
wire
out
WIDTH-10

 
parity_error
wire
out

 
stop_error
wire
out

 
data_avail
wire
out

 

 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_fifo.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`fifo default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81	133	jt_eaton
82	131	jt_eaton
83			`gen_verilog`
84			`104.0`
85			`none`
86			`common`
87			`./tools/verilog/gen_verilog`
88
89
90			`destination`
91	134	jt_eaton	`serial_rcvr_fifo`
92	131	jt_eaton
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109			`fs-common`
110
111
112
113
114			`../verilog/top.body`
115			`verilogSourcefragment`
116
117
118
119
120
121			`../verilog/fifo`
122			`verilogSourcefragment`
123
124
125
126
127
128
129
130
131
132			`fs-sim`
133
134
135
136	134	jt_eaton	`../verilog/copyright`
137	131	jt_eaton	`verilogSourceinclude`
138
139
140
141
142	134	jt_eaton	`../verilog/common/serial_rcvr_fifo`
143	131	jt_eaton	`verilogSourcemodule`
144
145
146	134	jt_eaton
147			`dest_dir`
148			`../views/sim/`
149			`verilogSourcelibraryDir`
150
151	131	jt_eaton
152
153	134	jt_eaton
154	131	jt_eaton
155
156
157
158			`fs-syn`
159
160
161
162
163	134	jt_eaton	`../verilog/copyright`
164	131	jt_eaton	`verilogSourceinclude`
165
166
167
168
169	134	jt_eaton	`../verilog/common/serial_rcvr_fifo`
170	131	jt_eaton	`verilogSourcemodule`
171
172
173	134	jt_eaton
174			`dest_dir`
175			`../views/syn/`
176			`verilogSourcelibraryDir`
177
178	131	jt_eaton
179	134	jt_eaton
180	131	jt_eaton
181
182
183
184
185
186
187
188
189
190
191
192
193
194			`Hierarchical`
195
196
197			`spirit:library="logic"`
198			`spirit:name="serial_rcvr"`
199			`spirit:version="fifo.design"/>`
200
201
202
203
204			`verilog`
205
206
207			`spirit:library="Testbench"`
208			`spirit:name="toolflow"`
209			`spirit:version="verilog"/>`
210
211
212
213
214
215
216
217
218			`commoncommon`
219			`Verilog`
220
221
222			`fs-common`
223
224
225
226
227
228
229			`sim:Simulation:`
230			`Verilog`
231
232
233			`fs-sim`
234
235
236
237
238
239			`syn:Synthesis:`
240			`Verilog`
241
242
243			`fs-syn`
244
245
246
247
248
249			`doc`
250
251
252			`spirit:library="Testbench"`
253			`spirit:name="toolflow"`
254			`spirit:version="documentation"/>`
255
256			`:Documentation:`
257			`Verilog`
258
259
260
261
262
263
264
265
266
267
268
269
270
271			`edge_enable`
272			`wire`
273			`in`
274
275
276			`parity_enable`
277			`wire`
278			`in`
279
280
281			`parity_type`
282			`wire`
283			`in`
284
285
286			`parity_force`
287			`wire`
288			`in`
289
290
291
292
293
294			`pad_in`
295			`wire`
296			`in`
297
298
299			`rcv_stb`
300			`wire`
301			`in`
302
303
304			`data_out`
305			`wire`
306			`out`
307			`WIDTH-10`
308
309
310			`parity_error`
311			`wire`
312			`out`
313
314
315			`stop_error`
316			`wire`
317			`out`
318
319
320			`data_avail`
321			`wire`
322			`out`
323
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