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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_def_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
serial_rcvr
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      serial_rcvr_def_tb
    
  

 
 
 
 

 
 
 

 
 
 
 
       
 
 
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="serial_rcvr"
                                   spirit:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="serial_rcvr"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
      
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/serial_rcvr_def_tb
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/serial_rcvr_def_tb
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`destination`
60	134	jt_eaton	`serial_rcvr_def_tb`
61	131	jt_eaton
62
63
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82			`Params`
83
84
85			`spirit:library="logic"`
86			`spirit:name="serial_rcvr"`
87			`spirit:version="def_dut.params"/>`
88
89
90
91
92			`Bfm`
93
94			`spirit:library="logic"`
95			`spirit:name="serial_rcvr"`
96			`spirit:version="bfm.design"/>`
97
98
99
100
101
102			`icarus`
103
104
105			`spirit:library="Testbench"`
106			`spirit:name="toolflow"`
107			`spirit:version="icarus"/>`
108
109
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111
112
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115			`commoncommon`
116			`Verilog`
117
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119			`fs-common`
120
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125			`sim:Simulation:`
126			`Verilog`
127
128
129			`fs-sim`
130
131
132
133
134
135
136			`lint:Lint:`
137			`Verilog`
138
139
140			`fs-lint`
141
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159			`fs-common`
160
161
162
163			`../verilog/top.ext`
164			`verilogSourcefragment`
165
166
167
168
169
170
171
172			`fs-sim`
173
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176	134	jt_eaton	`../verilog/common/serial_rcvr_def_tb`
177	131	jt_eaton	`verilogSourcemodule`
178
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189			`fs-lint`
190
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193	134	jt_eaton	`../verilog/common/serial_rcvr_def_tb`
194	131	jt_eaton	`verilogSourcemodule`
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_def_tb.xml] - Blame information for rev 134