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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [componentCfg.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
logic
uart
 
 
2
_
_
_
VARIANT
 
 

 
/doc
 

 
 
 
 
 

 
 
uart/sim
 
 
 
 
 
 

 
 

uart_def_tb
def_tb

    PERIOD40
    TIMEOUT100000


  
  uart_defTB.test.dut
  


  icaruscoverage


 
 

uart_rx_tb
rx_tb

    PERIOD40
    TIMEOUT100000


  
  uart_rxTB.test.dut
  


  icaruscoverage


 
 
 

uart_tx_tb
tx_tb

    PERIOD40
    TIMEOUT100000


  
  uart_txTB.test.dut
  


  icaruscoverage


 
 
 
 
 

uart_rxtx_tb
rxtx_tb

    PERIOD40
    TIMEOUT100000


  icarus


 
 
 
 
 
 

uart_def_lint
def_lint

  rtl_check


 
 

uart_rx_lint
rx_lint

  rtl_check


 
 
 

uart_tx_lint
tx_lint

  rtl_check


 
 

uart_rxtx_lint
rxtx_lint

  rtl_check


 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 

 

default
uart_def_lint

 

divide
uart_def_lint

DIV1


 

rx_default
uart_rx_lint

RX_FIFO_SIZE4
RX_FIFO_WORDS16


 

tx_default
uart_tx_lint

TX_FIFO_SIZE4
TX_FIFO_WORDS16


 

rxtx_default
uart_rxtx_lint

TX_FIFO_SIZE3
TX_FIFO_WORDS8
RX_FIFO_SIZE4
RX_FIFO_WORDS16


 

 
 
 
 
 
 

 

default
uart_def_tb

TIMEOUT3000000


 

divide
uart_def_tb

DIV1
TIMEOUT3000000


 

rx_default
uart_rx_tb

RX_FIFO_SIZE4
RX_FIFO_WORDS16
TIMEOUT3000000


 

tx_default
uart_tx_tb

TX_FIFO_SIZE4
TX_FIFO_WORDS16
TIMEOUT3000000


 

rxtx_default
uart_rxtx_tb

TX_FIFO_SIZE3
TX_FIFO_WORDS8
RX_FIFO_SIZE4
RX_FIFO_WORDS16
TIMEOUT3000000


 

 

 
 
 
 

 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [componentCfg.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`logic`
12			`uart`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20
21
22
23
24			`/doc`
25
26
27
28
29
30
31
32
33
34
35			`uart/sim`
36
37
38
39
40
41
42
43
44
45
46			`uart_def_tb`
47			`def_tb`
48
49			`PERIOD40`
50			`TIMEOUT100000`
51
52
53
54			`uart_defTB.test.dut`
55
56
57
58			`icaruscoverage`
59
60
61
62
63
64			`uart_rx_tb`
65			`rx_tb`
66
67			`PERIOD40`
68			`TIMEOUT100000`
69
70
71
72			`uart_rxTB.test.dut`
73
74
75
76			`icaruscoverage`
77
78
79
80
81
82
83			`uart_tx_tb`
84			`tx_tb`
85
86			`PERIOD40`
87			`TIMEOUT100000`
88
89
90
91			`uart_txTB.test.dut`
92
93
94
95			`icaruscoverage`
96
97
98
99
100
101
102
103
104			`uart_rxtx_tb`
105			`rxtx_tb`
106
107			`PERIOD40`
108			`TIMEOUT100000`
109
110
111			`icarus`
112
113
114
115
116
117
118
119
120
121			`uart_def_lint`
122			`def_lint`
123
124			`rtl_check`
125
126
127
128
129
130			`uart_rx_lint`
131			`rx_lint`
132
133			`rtl_check`
134
135
136
137
138
139
140			`uart_tx_lint`
141			`tx_lint`
142
143			`rtl_check`
144
145
146
147
148
149			`uart_rxtx_lint`
150			`rxtx_lint`
151
152			`rtl_check`
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175			`default`
176			`uart_def_lint`
177
178
179
180			`divide`
181			`uart_def_lint`
182
183			`DIV1`
184
185
186
187
188			`rx_default`
189			`uart_rx_lint`
190
191			`RX_FIFO_SIZE4`
192			`RX_FIFO_WORDS16`
193
194
195
196
197			`tx_default`
198			`uart_tx_lint`
199
200			`TX_FIFO_SIZE4`
201			`TX_FIFO_WORDS16`
202
203
204
205
206			`rxtx_default`
207			`uart_rxtx_lint`
208
209			`TX_FIFO_SIZE3`
210			`TX_FIFO_WORDS8`
211			`RX_FIFO_SIZE4`
212			`RX_FIFO_WORDS16`
213
214
215
216
217
218
219
220
221
222
223
224
225
226			`default`
227			`uart_def_tb`
228
229			`TIMEOUT3000000`
230
231
232
233
234			`divide`
235			`uart_def_tb`
236
237			`DIV1`
238			`TIMEOUT3000000`
239
240
241
242
243			`rx_default`
244			`uart_rx_tb`
245
246			`RX_FIFO_SIZE4`
247			`RX_FIFO_WORDS16`
248			`TIMEOUT3000000`
249
250
251
252
253			`tx_default`
254			`uart_tx_tb`
255
256			`TX_FIFO_SIZE4`
257			`TX_FIFO_WORDS16`
258			`TIMEOUT3000000`
259
260
261
262
263			`rxtx_default`
264			`uart_rxtx_tb`
265
266			`TX_FIFO_SIZE3`
267			`TX_FIFO_WORDS8`
268			`RX_FIFO_SIZE4`
269			`RX_FIFO_WORDS16`
270			`TIMEOUT3000000`
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
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288