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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 rxd_data_avail
  
  
  
    
 
      
        IRQ
        rxd_data_avail_IRQ
      
 
    
 
 
 
 
 txd_buffer_empty
  
  
  
    
 
      
        NIRQ
        txd_buffer_empty_NIRQ
      
 
    
 
 
 
 
 

 
 
 

 
 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
SIZE8
DIV0
DIV_SIZE4

 
 
 
 

 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72			`uart`
73
74
75
76
77
78
79			`txd_pad_out`
80			`txd_pad_out`
81
82
83
84
85			`rxd_pad_in`
86			`rxd_pad_in`
87
88
89
90
91
92
93
94			`rxd_data_avail`
95
96
97
98
99
100
101			`IRQ`
102			`rxd_data_avail_IRQ`
103
104
105
106
107
108
109
110			`txd_buffer_empty`
111
112
113
114
115
116
117			`NIRQ`
118			`txd_buffer_empty_NIRQ`
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140			`gen_verilog_sim`
141			`104.0`
142			`none`
143			`:Simulation:`
144			`./tools/verilog/gen_verilog`
145
146
147			`destination`
148			`top.out.sim`
149
150
151			`dest_dir`
152			`../verilog`
153
154
155
156
157
158
159			`gen_verilog_syn`
160			`104.0`
161			`none`
162			`:Synthesis:`
163			`./tools/verilog/gen_verilog`
164
165
166			`destination`
167			`top.out.syn`
168
169
170			`dest_dir`
171			`../verilog`
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189			`fs-sim`
190
191
192
193			`../verilog/copyright.v`
194			`verilogSourceinclude`
195
196
197
198
199
200			`../verilog/sim/top.out.sim`
201			`verilogSourcemodule`
202
203
204
205
206			`../verilog/top.body`
207			`verilogSourcefragment`
208
209
210
211
212			`../verilog/top.sim`
213			`verilogSourcefragment`
214
215
216
217
218
219
220
221
222			`fs-syn`
223
224
225
226			`../verilog/copyright.v`
227			`verilogSourceinclude`
228
229
230
231
232
233			`../verilog/syn/top.out.syn`
234			`verilogSourcemodule`
235
236
237
238
239			`../verilog/top.body`
240			`verilogSourcefragment`
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261			`Hierarchical`
262
263
264			`spirit:library="logic"`
265			`spirit:name="uart"`
266			`spirit:version="def.design"/>`
267
268
269
270
271			`verilog`
272
273
274			`spirit:library="Testbench"`
275			`spirit:name="toolflow"`
276			`spirit:version="verilog"/>`
277
278
279
280
281
282
283
284
285			`sim:Simulation:`
286
287			`Verilog`
288
289
290			`fs-sim`
291
292
293
294
295			`syn:Synthesis:`
296
297			`Verilog`
298
299
300			`fs-syn`
301
302
303
304
305
306			`doc`
307
308
309			`spirit:library="Testbench"`
310			`spirit:name="toolflow"`
311			`spirit:version="documentation"/>`
312
313			`:Documentation:`
314			`Verilog`
315
316
317
318
319
320
321
322
323
324
325
326
327
328			`PRESCALE5'b01100`
329			`PRE_SIZE5`
330			`SIZE8`
331			`DIV0`
332			`DIV_SIZE4`
333
334
335
336
337
338
339
340			`parity_enable`
341			`wire`
342			`in`
343
344
345			`divider_in`
346			`wire`
347			`in`
348			`DIV_SIZE-10`
349
350
351			`cts_pad_in`
352			`wire`
353			`in`
354
355
356			`rts_pad_out`
357			`reg`
358			`out`
359
360
361
362			`cts_out`
363			`reg`
364			`out`
365
366
367			`rts_in`
368			`wire`
369			`in`
370
371
372			`txd_parity`
373			`wire`
374			`in`
375
376
377			`txd_force_parity`
378			`wire`
379			`in`
380
381
382			`txd_load`
383			`wire`
384			`in`
385
386
387			`txd_break`
388			`wire`
389			`in`
390
391
392			`txd_data_in`
393			`wire`
394			`in`
395			`SIZE-10`
396
397
398			`txd_buffer_empty`
399			`wire`
400			`out`
401
402
403			`rxd_data_avail_stb`
404			`wire`
405			`in`
406
407
408			`rxd_data_avail`
409			`wire`
410			`out`
411
412
413			`rxd_parity`
414			`wire`
415			`in`
416
417
418			`rxd_force_parity`
419			`wire`
420			`in`
421
422
423			`rxd_data_out`
424			`wire`
425			`out`
426			`SIZE-10`
427
428
429			`rxd_parity_error`
430			`wire`
431			`out`
432
433
434			`rxd_stop_error`
435			`wire`
436			`out`
437
438
439
440
441
442
443
444
445
446
447