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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 rxd_data_avail
  
  
  
    
 
      
        IRQ
        rxd_data_avail_IRQ
      
 
    
 
 
 
 
 txd_buffer_empty
  
  
  
    
 
      
        NIRQ
        txd_buffer_empty_NIRQ
      
 
    
 
 
 
 
 

 
 
 

 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      uart_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_def
    
  

 
 
 
 

 
 
  
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/uart_def
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/uart_def
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
   
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 
 
 

 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72			`uart`
73
74
75
76
77
78
79			`txd_pad_out`
80			`txd_pad_out`
81
82
83
84
85			`rxd_pad_in`
86			`rxd_pad_in`
87
88
89
90
91
92
93
94			`rxd_data_avail`
95
96
97
98
99
100
101			`IRQ`
102			`rxd_data_avail_IRQ`
103
104
105
106
107
108
109
110			`txd_buffer_empty`
111
112
113
114
115
116
117			`NIRQ`
118			`txd_buffer_empty_NIRQ`
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138			`gen_verilog_sim`
139			`104.0`
140			`none`
141			`:Simulation:`
142			`./tools/verilog/gen_verilog`
143
144
145			`destination`
146	134	jt_eaton	`uart_def`
147	131	jt_eaton
148
149
150
151
152
153			`gen_verilog_syn`
154			`104.0`
155			`none`
156			`:Synthesis:`
157			`./tools/verilog/gen_verilog`
158
159
160			`destination`
161	134	jt_eaton	`uart_def`
162	131	jt_eaton
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179			`fs-sim`
180
181
182
183			`../verilog/copyright.v`
184			`verilogSourceinclude`
185
186
187
188
189
190	134	jt_eaton	`../verilog/sim/uart_def`
191	131	jt_eaton	`verilogSourcemodule`
192
193
194
195
196			`../verilog/top.body`
197			`verilogSourcefragment`
198
199
200
201
202			`../verilog/top.sim`
203			`verilogSourcefragment`
204
205
206	134	jt_eaton
207			`dest_dir`
208			`../views/sim/`
209			`verilogSourcelibraryDir`
210
211	131	jt_eaton
212	134	jt_eaton
213
214
215
216	131	jt_eaton
217
218
219
220
221			`fs-syn`
222
223
224
225			`../verilog/copyright.v`
226			`verilogSourceinclude`
227
228
229
230
231
232	134	jt_eaton	`../verilog/syn/uart_def`
233	131	jt_eaton	`verilogSourcemodule`
234
235
236
237
238			`../verilog/top.body`
239			`verilogSourcefragment`
240
241
242
243	134	jt_eaton
244			`dest_dir`
245			`../views/syn/`
246			`verilogSourcelibraryDir`
247
248	131	jt_eaton
249
250	134	jt_eaton
251	131	jt_eaton
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266			`Hierarchical`
267
268
269			`spirit:library="logic"`
270			`spirit:name="uart"`
271			`spirit:version="def.design"/>`
272
273
274
275
276			`verilog`
277
278
279			`spirit:library="Testbench"`
280			`spirit:name="toolflow"`
281			`spirit:version="verilog"/>`
282
283
284
285
286
287
288
289
290			`sim:Simulation:`
291
292			`Verilog`
293
294
295			`fs-sim`
296
297
298
299
300			`syn:Synthesis:`
301
302			`Verilog`
303
304
305			`fs-syn`
306
307
308
309
310
311			`doc`
312
313
314			`spirit:library="Testbench"`
315			`spirit:name="toolflow"`
316			`spirit:version="documentation"/>`
317
318			`:Documentation:`
319			`Verilog`
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336			`parity_enable`
337			`wire`
338			`in`
339
340
341			`divider_in`
342			`wire`
343			`in`
344			`DIV_SIZE-10`
345
346
347			`cts_pad_in`
348			`wire`
349			`in`
350
351
352			`rts_pad_out`
353			`reg`
354			`out`
355
356
357
358			`cts_out`
359			`reg`
360			`out`
361
362
363			`rts_in`
364			`wire`
365			`in`
366
367
368			`txd_parity`
369			`wire`
370			`in`
371
372
373			`txd_force_parity`
374			`wire`
375			`in`
376
377
378			`txd_load`
379			`wire`
380			`in`
381
382
383			`txd_break`
384			`wire`
385			`in`
386
387
388			`txd_data_in`
389			`wire`
390			`in`
391			`SIZE-10`
392
393
394			`txd_buffer_empty`
395			`wire`
396			`out`
397
398
399			`rxd_data_avail_stb`
400			`wire`
401			`in`
402
403
404			`rxd_data_avail`
405			`wire`
406			`out`
407
408
409			`rxd_parity`
410			`wire`
411			`in`
412
413
414			`rxd_force_parity`
415			`wire`
416			`in`
417
418
419			`rxd_data_out`
420			`wire`
421			`out`
422			`SIZE-10`
423
424
425			`rxd_parity_error`
426			`wire`
427			`out`
428
429
430			`rxd_stop_error`
431			`wire`
432			`out`
433
434
435
436
437
438
439
440
441
442
443