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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rx.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
rx
 

 
 slave_clk
  
  
      
  
 
    
      
        clk
        clk
      
    
        
      
 
 
  
 
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
          
      
  
 
 
 
 
 
 
 uart
  
  
      
  
 
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
        
      
 
 
  
 
 
 
 
 
 
 
 

 
 
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_rx
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_rx
    
  

 
 
 

 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/uart_rx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
   
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/uart_rx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
   
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 
 

 
        
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
  
 
              
              Hierarchical
                     Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rx.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`rx`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44	135	jt_eaton	`slave_clk`
45
46
47
48
49	131	jt_eaton
50	135	jt_eaton
51
52			`clk`
53			`clk`
54
55
56
57
58	131	jt_eaton
59
60	135	jt_eaton
61	131	jt_eaton
62	135	jt_eaton
63	131	jt_eaton
64
65	135	jt_eaton	`slave_reset`
66
67
68
69
70
71
72			`reset`
73			`reset`
74
75
76
77
78
79
80	131	jt_eaton
81
82
83
84
85	135	jt_eaton	`uart`
86
87
88
89
90	131	jt_eaton
91	135	jt_eaton
92	131	jt_eaton
93	135	jt_eaton
94			`txd_pad_out`
95			`txd_pad_out`
96
97	131	jt_eaton
98
99	135	jt_eaton
100			`rxd_pad_in`
101			`rxd_pad_in`
102
103	131	jt_eaton
104
105	135	jt_eaton
106
107
108
109
110	131	jt_eaton
111
112	135	jt_eaton
113	131	jt_eaton
114	135	jt_eaton
115	131	jt_eaton
116
117
118
119
120
121	135	jt_eaton
122	131	jt_eaton
123
124
125	135	jt_eaton
126	131	jt_eaton
127
128
129
130	135	jt_eaton
131			`gen_verilog_sim`
132			`104.0`
133			`none`
134			`:Simulation:`
135			`tools/verilog/gen_verilog`
136
137
138			`destination`
139			`uart_rx`
140
141
142
143	131	jt_eaton
144	135	jt_eaton
145			`gen_verilog_syn`
146			`104.0`
147			`none`
148			`:Synthesis:`
149			`tools/verilog/gen_verilog`
150
151
152			`destination`
153			`uart_rx`
154
155
156
157	131	jt_eaton
158
159
160	135	jt_eaton
161	131	jt_eaton
162
163
164
165	135	jt_eaton
166	131	jt_eaton
167	135	jt_eaton
168			`fs-sim`
169	131	jt_eaton
170	135	jt_eaton
171
172			`../verilog/copyright.v`
173			`verilogSourceinclude`
174
175	134	jt_eaton
176
177	135	jt_eaton
178
179			`../verilog/sim/uart_rx`
180			`verilogSourcemodule`
181
182	131	jt_eaton
183	135	jt_eaton
184
185			`../verilog/top.body`
186			`verilogSourcefragment`
187
188	131	jt_eaton
189	135	jt_eaton
190
191			`../verilog/top.sim`
192			`verilogSourcefragment`
193
194	131	jt_eaton
195
196	135	jt_eaton
197			`dest_dir`
198			`../views/sim/`
199			`verilogSourcelibraryDir`
200
201	131	jt_eaton
202
203
204	135	jt_eaton
205	131	jt_eaton
206	134	jt_eaton
207	135	jt_eaton
208			`fs-syn`
209	134	jt_eaton
210	135	jt_eaton
211
212			`../verilog/copyright.v`
213			`verilogSourceinclude`
214
215	134	jt_eaton
216	131	jt_eaton
217	135	jt_eaton
218
219			`../verilog/syn/uart_rx`
220			`verilogSourcemodule`
221
222	131	jt_eaton
223	135	jt_eaton
224
225			`../verilog/top.body`
226			`verilogSourcefragment`
227
228	131	jt_eaton
229
230	135	jt_eaton
231			`dest_dir`
232			`../views/syn/`
233			`verilogSourcelibraryDir`
234
235	131	jt_eaton
236
237
238	135	jt_eaton
239	131	jt_eaton
240
241
242
243
244
245	135	jt_eaton
246	131	jt_eaton
247
248
249
250
251	135	jt_eaton
252	131	jt_eaton
253	135	jt_eaton
254
255			`Hierarchical`
256
257
258
259	131	jt_eaton
260	135	jt_eaton
261
262
263
264
265
266
267			`Hierarchical`
268			`Hierarchical`
269
270
271
272
273			`verilog`
274
275
276			`ipxact:library="Testbench"`
277			`ipxact:name="toolflow"`
278			`ipxact:version="verilog"/>`
279
280
281
282
283
284
285
286
287
288			`sim:Simulation:`
289	131	jt_eaton
290	135	jt_eaton	`Verilog`
291
292
293			`fs-sim`
294
295
296	131	jt_eaton
297	135	jt_eaton
298			`syn:Synthesis:`
299	131	jt_eaton
300	135	jt_eaton	`Verilog`
301
302
303			`fs-syn`
304
305
306	131	jt_eaton
307	135	jt_eaton
308			`doc`
309
310
311			`ipxact:library="Testbench"`
312			`ipxact:name="toolflow"`
313			`ipxact:version="documentation"/>`
314
315			`:Documentation:`
316			`Verilog`
317
318	131	jt_eaton
319
320
321	135	jt_eaton
322	131	jt_eaton
323
324
325
326
327	135	jt_eaton
328	131	jt_eaton
329	135	jt_eaton	`parity_enable`
330			`wire`
331			`in`
332
333	131	jt_eaton
334	135	jt_eaton	`divider_in`
335			`wire`
336			`in`
337			`DIV_SIZE-10`
338
339	131	jt_eaton
340	135	jt_eaton	`cts_pad_in`
341			`wire`
342			`in`
343
344	131	jt_eaton
345	135	jt_eaton	`rts_pad_out`
346			`reg`
347			`out`
348
349	131	jt_eaton
350
351
352	135	jt_eaton	`cts_out`
353			`reg`
354			`out`
355
356	131	jt_eaton
357	135	jt_eaton	`rts_in`
358			`wire`
359			`in`
360
361	131	jt_eaton
362	135	jt_eaton	`txd_parity`
363			`wire`
364			`in`
365
366	131	jt_eaton
367	135	jt_eaton	`txd_force_parity`
368			`wire`
369			`in`
370
371	131	jt_eaton
372	135	jt_eaton	`txd_load`
373			`wire`
374			`in`
375
376	131	jt_eaton
377	135	jt_eaton	`txd_break`
378			`wire`
379			`in`
380
381	131	jt_eaton
382	135	jt_eaton	`txd_data_in`
383			`wire`
384			`in`
385			`SIZE-10`
386
387	131	jt_eaton
388	135	jt_eaton	`txd_buffer_empty`
389			`wire`
390			`out`
391
392	131	jt_eaton
393	135	jt_eaton	`rxd_data_avail_stb`
394			`wire`
395			`in`
396
397	131	jt_eaton
398	135	jt_eaton	`rxd_data_avail`
399			`wire`
400			`out`
401
402	131	jt_eaton
403	135	jt_eaton	`rxd_parity`
404			`wire`
405			`in`
406
407	131	jt_eaton
408	135	jt_eaton	`rxd_force_parity`
409			`wire`
410			`in`
411
412	131	jt_eaton
413	135	jt_eaton	`rxd_data_out`
414			`wire`
415			`out`
416			`SIZE-10`
417
418	131	jt_eaton
419	135	jt_eaton	`rxd_parity_error`
420			`wire`
421			`out`
422
423	131	jt_eaton
424	135	jt_eaton	`rxd_stop_error`
425			`wire`
426			`out`
427
428	131	jt_eaton
429	135	jt_eaton
430	131	jt_eaton
431	135	jt_eaton
432	131	jt_eaton
433
434
435
436
437
438	135	jt_eaton