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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rx.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
rx  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 
 rxd_data_avail
  
  
  
    
 
      
        IRQ
        rxd_data_avail_IRQ
      
 
    
 
 
 

 
 
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_rx
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_rx
    
  

 
 
 

 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/uart_rx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
   
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/uart_rx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
   
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="rx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rx.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`rx default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73			`uart`
74
75
76
77
78
79
80			`txd_pad_out`
81			`txd_pad_out`
82
83
84
85
86			`rxd_pad_in`
87			`rxd_pad_in`
88
89
90
91
92
93
94
95
96			`rxd_data_avail`
97
98
99
100
101
102
103			`IRQ`
104			`rxd_data_avail_IRQ`
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121			`gen_verilog_sim`
122			`104.0`
123			`none`
124			`:Simulation:`
125			`./tools/verilog/gen_verilog`
126
127
128			`destination`
129	134	jt_eaton	`uart_rx`
130	131	jt_eaton
131
132
133
134
135			`gen_verilog_syn`
136			`104.0`
137			`none`
138			`:Synthesis:`
139			`./tools/verilog/gen_verilog`
140
141
142			`destination`
143	134	jt_eaton	`uart_rx`
144	131	jt_eaton
145
146
147
148
149
150
151
152
153
154
155
156
157
158			`fs-sim`
159
160
161
162			`../verilog/copyright.v`
163			`verilogSourceinclude`
164
165
166
167
168
169	134	jt_eaton	`../verilog/sim/uart_rx`
170	131	jt_eaton	`verilogSourcemodule`
171
172
173
174
175			`../verilog/top.body`
176			`verilogSourcefragment`
177
178
179
180
181			`../verilog/top.sim`
182			`verilogSourcefragment`
183
184
185
186	134	jt_eaton
187			`dest_dir`
188			`../views/sim/`
189			`verilogSourcelibraryDir`
190
191	131	jt_eaton
192	134	jt_eaton
193
194	131	jt_eaton
195
196
197
198			`fs-syn`
199
200
201
202			`../verilog/copyright.v`
203			`verilogSourceinclude`
204
205
206
207
208
209	134	jt_eaton	`../verilog/syn/uart_rx`
210	131	jt_eaton	`verilogSourcemodule`
211
212
213
214
215			`../verilog/top.body`
216			`verilogSourcefragment`
217
218
219
220	134	jt_eaton
221			`dest_dir`
222			`../views/syn/`
223			`verilogSourcelibraryDir`
224
225
226
227
228	131	jt_eaton
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245			`Hierarchical`
246
247
248			`spirit:library="logic"`
249			`spirit:name="uart"`
250			`spirit:version="rx.design"/>`
251
252
253
254
255			`verilog`
256
257
258			`spirit:library="Testbench"`
259			`spirit:name="toolflow"`
260			`spirit:version="verilog"/>`
261
262
263
264
265
266
267
268
269
270			`sim:Simulation:`
271
272			`Verilog`
273
274
275			`fs-sim`
276
277
278
279
280			`syn:Synthesis:`
281
282			`Verilog`
283
284
285			`fs-syn`
286
287
288
289
290			`doc`
291
292
293			`spirit:library="Testbench"`
294			`spirit:name="toolflow"`
295			`spirit:version="documentation"/>`
296
297			`:Documentation:`
298			`Verilog`
299
300
301
302
303
304
305
306
307
308
309
310
311			`parity_enable`
312			`wire`
313			`in`
314
315
316			`divider_in`
317			`wire`
318			`in`
319			`DIV_SIZE-10`
320
321
322			`cts_pad_in`
323			`wire`
324			`in`
325
326
327			`rts_pad_out`
328			`reg`
329			`out`
330
331
332
333
334			`cts_out`
335			`reg`
336			`out`
337
338
339			`rts_in`
340			`wire`
341			`in`
342
343
344			`txd_parity`
345			`wire`
346			`in`
347
348
349			`txd_force_parity`
350			`wire`
351			`in`
352
353
354			`txd_load`
355			`wire`
356			`in`
357
358
359			`txd_break`
360			`wire`
361			`in`
362
363
364			`txd_data_in`
365			`wire`
366			`in`
367			`SIZE-10`
368
369
370			`txd_buffer_empty`
371			`wire`
372			`out`
373
374
375			`rxd_data_avail_stb`
376			`wire`
377			`in`
378
379
380			`rxd_data_avail`
381			`wire`
382			`out`
383
384
385			`rxd_parity`
386			`wire`
387			`in`
388
389
390			`rxd_force_parity`
391			`wire`
392			`in`
393
394
395			`rxd_data_out`
396			`wire`
397			`out`
398			`SIZE-10`
399
400
401			`rxd_parity_error`
402			`wire`
403			`out`
404
405
406			`rxd_stop_error`
407			`wire`
408			`out`
409
410
411
412
413
414
415
416
417
418
419
420