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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rxtx.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
rxtx  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 
 rxd_data_avail
  
  
  
    
 
      
        IRQ
        rxd_data_avail_IRQ
      
 
    
 
 
 
 
 txd_buffer_empty
  
  
  
    
 
      
        NIRQ
        txd_buffer_empty_NIRQ
      
 
    
 
 
 
 
 

 
 
 

 
 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.rxtx.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.rxtx.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/top.rxtx.sim
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.rxtx.syn
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
 
    
 
 
 
 
  
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="rxtx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
SIZE8
DIV0
DIV_SIZE4
TX_FIFO_SIZE3
TX_FIFO_WORDS8
RX_FIFO_SIZE3
RX_FIFO_WORDS8

 
 
 
 

 
 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rxtx.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`rxtx default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71			`uart`
72
73
74
75
76
77
78			`txd_pad_out`
79			`txd_pad_out`
80
81
82
83
84			`rxd_pad_in`
85			`rxd_pad_in`
86
87
88
89
90
91
92
93
94			`rxd_data_avail`
95
96
97
98
99
100
101			`IRQ`
102			`rxd_data_avail_IRQ`
103
104
105
106
107
108
109
110			`txd_buffer_empty`
111
112
113
114
115
116
117			`NIRQ`
118			`txd_buffer_empty_NIRQ`
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140			`gen_verilog_sim`
141			`104.0`
142			`none`
143			`:Simulation:`
144			`./tools/verilog/gen_verilog`
145
146
147			`destination`
148			`top.rxtx.sim`
149
150
151			`dest_dir`
152			`../verilog`
153
154
155
156
157
158			`gen_verilog_syn`
159			`104.0`
160			`none`
161			`:Synthesis:`
162			`./tools/verilog/gen_verilog`
163
164
165			`destination`
166			`top.rxtx.syn`
167
168
169			`dest_dir`
170			`../verilog`
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187			`fs-sim`
188
189
190
191			`../verilog/copyright.v`
192			`verilogSourceinclude`
193
194
195
196
197
198			`../verilog/sim/top.rxtx.sim`
199			`verilogSourcemodule`
200
201
202
203
204			`../verilog/top.body.tx`
205			`verilogSourcefragment`
206
207
208
209
210
211			`../verilog/top.sim`
212			`verilogSourcefragment`
213
214
215
216
217
218
219
220
221
222			`fs-syn`
223
224
225
226			`../verilog/copyright.v`
227			`verilogSourceinclude`
228
229
230
231
232
233			`../verilog/syn/top.rxtx.syn`
234			`verilogSourcemodule`
235
236
237
238
239			`../verilog/top.body.tx`
240			`verilogSourcefragment`
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260			`Hierarchical`
261
262
263			`spirit:library="logic"`
264			`spirit:name="uart"`
265			`spirit:version="rxtx.design"/>`
266
267
268
269
270			`verilog`
271
272
273			`spirit:library="Testbench"`
274			`spirit:name="toolflow"`
275			`spirit:version="verilog"/>`
276
277
278
279
280
281
282
283
284			`sim:Simulation:`
285
286			`Verilog`
287
288
289			`fs-sim`
290
291
292
293
294			`syn:Synthesis:`
295
296			`Verilog`
297
298
299			`fs-syn`
300
301
302
303
304
305			`doc`
306
307
308			`spirit:library="Testbench"`
309			`spirit:name="toolflow"`
310			`spirit:version="documentation"/>`
311
312			`:Documentation:`
313			`Verilog`
314
315
316
317
318
319
320
321
322
323
324
325
326
327			`PRESCALE5'b01100`
328			`PRE_SIZE5`
329			`SIZE8`
330			`DIV0`
331			`DIV_SIZE4`
332			`TX_FIFO_SIZE3`
333			`TX_FIFO_WORDS8`
334			`RX_FIFO_SIZE3`
335			`RX_FIFO_WORDS8`
336
337
338
339
340
341
342
343
344			`parity_enable`
345			`wire`
346			`in`
347
348
349			`divider_in`
350			`wire`
351			`in`
352			`DIV_SIZE-10`
353
354
355			`cts_pad_in`
356			`wire`
357			`in`
358
359
360			`rts_pad_out`
361			`reg`
362			`out`
363
364
365
366			`cts_out`
367			`reg`
368			`out`
369
370
371			`rts_in`
372			`wire`
373			`in`
374
375
376			`txd_parity`
377			`wire`
378			`in`
379
380
381			`txd_force_parity`
382			`wire`
383			`in`
384
385
386			`txd_load`
387			`wire`
388			`in`
389
390
391			`txd_break`
392			`wire`
393			`in`
394
395
396			`txd_data_in`
397			`wire`
398			`in`
399			`SIZE-10`
400
401
402			`txd_buffer_empty`
403			`wire`
404			`out`
405
406
407			`rxd_data_avail_stb`
408			`wire`
409			`in`
410
411
412			`rxd_data_avail`
413			`wire`
414			`out`
415
416
417			`rxd_parity`
418			`wire`
419			`in`
420
421
422			`rxd_force_parity`
423			`wire`
424			`in`
425
426
427			`rxd_data_out`
428			`wire`
429			`out`
430			`SIZE-10`
431
432
433			`rxd_parity_error`
434			`wire`
435			`out`
436
437
438			`rxd_stop_error`
439			`wire`
440			`out`
441
442
443
444
445
446
447
448
449
450